1.28 and 5.12 Gbps multi-channel twinax cable receiver ASICs for the ATLAS Inner Tracker Pixel Detector Upgrade
Chufeng Chen, Datao Gong, Suen Hou, Guangming Huang, Xing Huang, Szymon Kulis, Paul Leroux, Chonghan Liu, Tiankuan Liu, Paulo Moreira, Jefery Prinzie, Peilong Wang, Jingbo Ye
11.28 and 5.12 Gbps multi-channel twinax cable receiver ASICs for the ATLASInner Tracker Pixel Detector Upgrade
Chufeng Chen a,b , Datao Gong a, ∗ , Suen Hou c , Guangming Huang b , Xing Huang a,b , Szymon Kulis d , Paul Leroux e ,Chonghan Liu a , Tiankuan Liu a , Paulo Moreira d , Je ff ery Prinzie e , Peilong Wang a , Jingbo Ye a a Department of Physics, Southern Methodist University, Dallas, TX 75275, USA b Department of Physics, Central China Normal University, Wuhan, Hubei 430079, P.R. China c Institute of Physics, Academia Sinica, Taiwan d Microelectronic group at CERN, 1211 Geneva 23, Switzerland e KU Leuven, Leuven, Belgium
Abstract
We present two prototypes of a gigabit transceiver ASIC, GBCR1 and GBCR2, both designed in a 65-nm CMOStechnology for the ATLAS Inner Tracker Pixel Detector readout upgrade.The first prototype, GBCR1, has four upstream receiver channels and one downstream transmitter channel withpre-emphasis. Each upstream channel receives the data at 5.12 Gbps through a 5 meter AWG34 Twinax cable froman ASIC driver located on the pixel module and restores the signal from the high frequency loss due to the low masscable. The signal is retimed by a recovered clock before it is sent to the optical transmitter VTRx + . The downstreamdriver is designed to transmit the 2.56 Gbps signal from lpGBT to the electronics on the pixel module over the samecable. The peak-peak jitter (throughout the paper jitter is always peak-peak unless specified) of the restored signal is35.4 ps at the output of GBCR1, and 138 ps for the downstream channel at the cable ends. GBCR1 consumes 318mW and is tested.The second prototype, GBCR2, has seven upstream channels and two downstream channels. Each upstream channelworks at 1.28 Gbps to recover the data directly from the RD53B ASIC through a 1 meter custom FLEX cable followedby a 6 meter AWG34 Twinax cable. The equalized signal of each upstream channel is retimed by an input 1.28 GHzphase programmable clock. Compared with the signal at the FLEX input, the additional jitter of the equalized signalis about 80 ps when the retiming logic is o ff . When the retiming logic is on, the jitter is 50 ps at GBCR2 output,assuming the 1.28 GHz retiming clock is from lpGBT. The downstream is designed to transmit the 160 Mbps signalfrom lpGBT through the same cable connection to RD53B and the jitter is about 157 ps at the cable ends. GBCR2consumes about 150 mW when the retiming logic is o ff . This design was submitted in November 2019. Keywords: Optical detector readout concepts , Array optical transmission , Front-end electronics for detectorreadout , Radiation tolerant , Lasers Driver ASIC2010 MSC:
1. Introduction
In the Phase-II upgrade of the ATLAS inner tracker(ITk) Pixel Detector, the pixel sensors are to be read outby the RD53B ASIC and its output is to be transmit-ted to a location meters away from the sensors whereit is to be converted to optical for further transmis-sion through optical fibers [1]. The output data rate ofRD53B is 1.28 Gbps. The readout scheme evolves from ∗ Corresponding author
Email address: [email protected] (Datao Gong) a data aggregator ASIC on the pixel module to send4*1.28 = + will be usedto convert between electrical and optical signals. Thelatter becomes the baseline of the sensor readout, tak-ing into consideration of ASIC development status, de-tector material budget, powering and implementation.In this baseline design to place the opto-box (which Preprint submitted to Nuclear Instruments and Methods in Physics Research Section A August 25, 2020 a r X i v : . [ phy s i c s . i n s - d e t ] A ug ouses lpGBT, VTRx + and other electronics) metersaway from the sensor is also to avoid the high radia-tion environment near the interaction point and to of-fer relatively easy access to service and repairing. Inboth schemes one of the challenges is to transmit giga-bit persecond data over low-mass electrical cables. Inthe chosen AWG34 Twinax cable with a length from 3to 6 meters the high-frequency loss is significant andthe eye-diagram is fully closed even at 1.28 Gbps. Tocompensate this loss, an equalizer ASIC is needed atthe cable ends. The peaking strength needs to be pro-grammable cope with the system implementation wherecable length varies. Although the opto-box is metersaway from the interaction point, it is still in radiationenvironment. Beside the radiation-tolerant requirement,the power budget of the equalizer chip is also tightwhich makes the design more challenging.We present two prototype chips in this paper, bothused to equalize the high-speed data signals over thelow-mass cables. GBCR1 has 4 upstream channels eachworking at 5.12 Gbps, corresponding to the initial datatransmission scheme [1]. The chip has been success-fully tested at laboratory and in irradiation. GBCR2is for the revised readout scheme which is now thebaseline. GBCR2 has 7 upstream channels each at1.28 Gbps, resulting tighter power consumption of eachchannel. Both ASICs have downstream cable driverchannels to send signals to the electronics on the pixelmodule.
2. Design and Test for GBCR1
The initial scheme of data transmission between thepixel module and opto-box is based on a concept of ”ac-tive cable” in which two dedicated ASICs, the Aggrega-tor and GBCR1 are at the cable ends. Figure 1 shows adiagram of this scheme. The Aggregator combines thefour 1.28 Gbps data lanes from the FE modules [2] andtransmits data at 5.12 Gbps to GBCR1 through a 5 meterAWG34 Twinax cable. GBCR1 receives these signalsand recovers them to meet the requirements of the opti-cal transmitter VTRx + [3] [4] in the opto-box located atthe patch-panel 1 (PP1). With the high-frequency losscompensated by GBCR1, the active cable performs as awide-band cable.The block diagram of GBCR1 is shown in Figure2. There are four upstream channels, one downstreamchannel, an Inter-Integrated Circuit (I2C) slave andan Automatic Frequency Calibration (AFC) module inGBCR1. Among these four upstream channels, thereare 3 baseline channels and 1 test channel which is notpresented in this paper. Each upstream channel operates Figure 1: The original ITk Readout System Plan at 5.12 Gbps data and consists of a Continuous TimeLinear Equalizer (CTLE), a Limiting Amplifier (LA),a Clock Data Recovery (CDR) and a Current ModeLogic (CML) driver. The downstream channel includes3 stages of LAs, a passive attenuator, a pre-emphasizerand an output driver with data rate at 2.56 Gbps. TheAFC module [5] is used to calibrate the VCO in eachupstream channel to ensure it works perfectly at 5.12GHz [6]. The I2C slave provides all configuring andcontrol signals of the whole chip.
Figure 2: Block Diagram of GBCR1
The equalizer used in GBCR1 is based on a CTLEstructure. The passive resistor and capacitor create azero and a pole in the transfer function to compensatefor channel loss [7]. CTLE behaves as a high-pass fil-ter to compensate the undesired low-pass e ff ect of thechannel at high frequency. The active CTLE with RCcan provide high-frequency gain peaking by means ofa real zero [8]. The zero and pole are described by thefollowing formulae: ω Z = R S C S (1) ω p = + g m R S R S C S (2)The equalization strength is determined by the ratioof the zero and the pole, as described in formula 3, EqualizationS trength = ω Z ω p = + R S C S R S and C S in the CTLE are pro-grammable in order to adjust the zero, pole and equal-ization for the optimal results in di ff erent situations. Asthe solid line in Figure 3(b) shows, the signal loss atthe Nyquist frequency, 2.56 GHz, of the cable is about -16.5 dB . The dotted line shows the frequency responseof the equalizer with the peaking strength of 16.9 dB.After the equalization, the overall frequency response isflat as shown with the dash line. As the multiple CTLEstages create multiple order poles above 2.56 GHz, thefrequency response curve falls rapidly beyond this fre-quency. Because the signal is saturated after the laststage of output bu ff er which bandwidth is 4.2 GHz,much higher than 2.56 GHz, the output signal rise andfall time is about 40 ps, much faster than the single-frequency of the Nyquist frequency. Figure 3: Schematic of a CTLE (a) and AC response of the equalizer(b)
To further reduce the ISI jitter due to the cable, a CDRis used to recover the clock in the signal and retime theoutput. The CDR [9] in GBCR1 is adapted from lpGBT[10]. The original CDR works for 2.56 Gbps data onlyand the VCO is locked at 5.12 GHz. We remove thefrequency detector to release the frequency feedback inthe loop control so that it also works at 5.12 Gbps datarate [11]. The LC-VCO, the core of the CDR, has lowphase noise but its oscillating range is narrow. A pro-grammable capacitor bank is used to extend its oscil-lating range. The AFC is needed to select the optimalsetting for the capacitor bank to ensure the operation at5.12 GHz.CML driver [12], a di ff erential amplifier with a loadresistance of 50 Ohm, with a bandwidth of 4.2 GHz andan amplitude larger than 200 mV to meet the eRx re-quirements of lpGBT which is 140 mV, is used to trans-mit the recovered signals and drive the VTRx + opticalmodule in the next stage. A 2.56 Gbps data from VTRx + is transmitted tothe front-end module through the same electrical cable as the upstream channel. The downstream channel inGBCR1 is designed to pre-emphasize these signals be-fore sending them through the cable which causes a 11.7dB loss at the Nyquist frequency of 1.28 GHz. The pre-emphasizer stage [13], which has the CTLE structure isemployed with up to 13 dB peaking gain. The gain ofthe passive attenuator is -3.5 dB to attenuate the max-imum amplitude signals from the former LA stages toavoid the saturation of the signal. The AC response ofdownstream channel is shown in Figure 4. Figure 4: AC response of downstream channel
The test block diagram and the actual test bench arein Figure 5. In the test we used the only 6 meter AWG34Twinax cable that we had. We have updated the simula-tion with this 6 meter cable in order to compare it withthe test results.
Figure 5: Block Diagram of GBCR1 Test Bench
Figure 6 shows the eye diagrams at di ff erent test-ing points of an upstream channel. As shown in Fig-ure 6(a), when the data from signal generator passesthrough the 6 meter cable, the eye is completely closed.The eye opens again after being recovered by the equal-izer. When the CDR is o ff and the retiming is bypassed,the peak-peak jitter is 79 ps and the random jitter is 4.33s (RMS) under the resistance setting of 0 and the ca-pacitance setting of 3 of the equalizers. When the CDRis turned on, the retiming circuit reduces the peak-peakjitter to 35 ps and the random jitter 1.5 ps (RMS). TheCDR significantly reduces the jitter at the cost of 44mW, a 61% increase of the channel power.We also observed some significant DC o ff set in theoutput eye diagram as shown in Figure 6(d). We believethe DC o ff set is from the mismatch in the chip and weconfirm that in the simulation. To suppress the jitterfrom the DC o ff set, a DC o ff set cancellation circuit isemployed in GBCR2. Figure 6: Eye diagrams (a) after the 6m Twinax cable and before theGBCR, (b) after the GBCR (CDR is o ff ) (c), after the GBCR (CDR ison) (d) after the GBCR, one example with obvious DC o ff set Figure 7 shows the results of bit error rate (BER),which are obtained by scanning the resistance setting asthe capacitance setting is fixed at 4. When the value ofresistance setting in CTLEs is from 0 to 7, there are 0errors during the 20 minute test. The BER is estimatedto be below 3.7*10 − with 90% confidence level whichmeets the specification of 1*10 − . As the resistancesetting grows, the BER increases. These results indi-cate that, when the equalizers in the upstream channelsare properly configured, GBCR1 can recover the datacorrectly.The downstream channel has been tested with thesame cable. Figure 8 shows the eye diagrams of thedownstream channel before and after the Twinax cable.The overshoot, as shown in Figure 8(a), in the eye di-agram before the cable, is obvious because of the pre-emphasis. After the cable, the eye diagram, as shown inFigure 8(b), is still open. The measured peak-peak jitteris 138 ps and the random jitter is 4.1 ps (RMS), consis-tent with the simulation results of the 6 meter cable. Figure 7: BER Test ResultsFigure 8: Eye diagrams before (a) and after the Twinax cable (b)
GBCR1 has also been irradiated with gamma from aCo-60 source. It survives the total ionizing dose up to200 kGy which is the maximum required dose. The chipwas kept powered on during the entire irradiation. Wedid not observe significant degradation in the amplitude.The jitter of upstream channel changed no more than 2ps after the radiation in both cases of CDR on and o ff .
3. GBCR2
In the baseline of the data transmission scheme, asshown in Figure 9, the sensor readout ASIC RD53B[14] sends data through the FLEX cable and the AWG34Twinax cable with various length, at a data rate of 1.28Gbps per channel. The FLEX ranges from 0.1 to 1 me-ter and the Twinax from 3 to 6 meters. This leads todi ff erent high frequency loss. To cope with it, the equal-ization strength in GBCR2 needs to be programmable. Figure 9: Updated ITk Readout Plan
Figure 10 shows the block diagram of GBCR2. Thereare seven uplink channels and two downlink channels.Compared with GBCR1, the CDR module is removed4n this design because it consumes 36.4 mA each whichis too much for the power budget in the new design of7 channels. Instead, an external clock of 1.28 GHz witha phase shifter is used to achieve the retiming function.All these uplink channels share the same phase shifter[15][16] which is adapted from lpGBT. An I2C slaveprovides configure and control signals for all the chan-nels in GBCR2.
Figure 10: The Block Diagram of GBCR2
As seen in Figure 10, the uplink channel consists of apassive attenuator, an equalizer, retiming logic, DC o ff -set cancellation circuits and CML driver. The passiveattenuator is programmable to attenuate the signal fromRD53B to avoid the saturation distortion in case the sig-nal amplitude is large. The equalizer has a high-passdi ff erential stage to compensate the signal loss. The DCcancellation circuit is designed to reduce the DC o ff -set caused by mismatch in the amplifiers. The retimingcircuit of each channel shares one phase shifter but thesampling clock phase of each channel is programmableindependently. A CML driver is used to send the recov-ered data to the eRx module in lpGBT.From the frequency response curve of the signal lossin the worst case (1 meter FLEX cable and 6 meterTwinax cable), we divided the curve into 3 ranges, asshown in Figure 11. In the high frequency range from0.4-1.3 GHz, the decay slope is 27.3 dB / dec. In the mid-dle frequency range from 0.2 to 0.4 GHz, it is about14.3 dB / dec, which is about half of the high-frequencyrange. In the low frequency range from 0.08 to 0.2 GHz,the decay slope is 8.5 dB / dec, about one third of thehigh frequency range. In this case, the multiple stagesof CTLE are adopted to compensate the loss due to thelong-distance transmission. But for the high frequencypart, the slope is too steep to be compensated with oneorder zero. We design a 3 identical CTLE stages tocompensate with 3 order zero for high frequency range.For the medium and low frequency parts, each of them just employs one CTLE stage to recover the signal lossin their range respectively. The entire equalizer stagecan provide 30 dB peaking strength at most. As theCTLE in GBCR1, the resistance of Rs in GBCR2 isprogrammable by 4 control bits to tune the zero posi-tion and the equalization. But the capacitance of Cs isconstant in order to keep up the pole position. Figure 11: Simulation of Cable Loss based on 1-m flex model and6-m Twinax model in series
In the multiple-stage structure, we keep the DCgain of each stage around 0 dB and amplify the high-frequency signal only. After recovered by the equalizersin uplink channel, the frequency response of the equal-izer output is shown in Figure 12. The gain is 12.2 dBwhen using the shortest cable and it will be -5.2 dB inthe situation of the longest cable.
Figure 12: AC Response of the recovered signals
As discussed in Section 2, a DC o ff set cancellationcircuit is needed to suppress the DC o ff set from mis-match. The circuit is shown in Figure 13. The highfrequency component is removed by a low pass RC fil-ter and the DC o ff set is amplified and fed back to theinput stage of LA to adjust and cancel the DC o ff set.The DC o ff set cancellation circuit causes a low cut-o ff frequency in the main signal path. The low cut-o ff fre-quency is 115 kHz, which has no e ff ect on the data en-coded in 64b /
66b line code. Because the gain of thefeedback amplifier is 100 dB, we expect that the DCo ff set is highly suppressed.In the GBCR1 design, the CML driver operates at5 igure 13: DC-o ff set Cancellation Circuit ff -set cancellation circuit is o ff , the jitter of final output ofthe uplink channel is below 100 ps in simulations for allthe process corners. The typical eye diagram is shownin Figure 14, in which the jitter is about 65.9 ps. Figure 14: Simulation results of before (a) and after recovered by theuplink channel (b)
The downlink channel, which works at 160 Mbps, isa part of the command link, which includes the eTx inlpGBT, the downlink channel in GBCR2, and the CDRin RD53B. It is important to suppress the ISI jitter ofthe input signal of the CDR in RD53B because the re-covered clock signal is also used for high-speed datatransmission up to 1.28 Gbps. The GBCR2 downlinkchannel receives the 160 Mbps data from lpGBT, pre-emphasize them and then transmit the data to RD53Bthrough the same cables as the ones used in uplink chan-nels. As shown in Figure 10, this channel also consistsof a programmable passive attenuator, a pre-emphasizer,a low-pass filter circuit and a CML output driver. The pre-emphasizer has two stages of CTLE which is thesame structure as used in the uplink channel. But be-cause the data rate is much lower, the parameters in thedownlink channel are redesigned. Its zero is at 40 MHzand the pole is at 120 MHz. There is also a 3-bit con-trol in the pre-emphasizer stage to adjust the peakingstrength which is up to 14.8 dB.Even in the transmission situation with the longestcables, the downstream channel significantly reduce theISI jitter from 500 ps to 157 ps. The eye diagrams beforeand after the cables are shown in Figure 15.
Figure 15: Simulation results of before (a) and after (b) the cables ofthe downlink channel
As a conclusion, based on simulation GBCR2 willwork well to receive and transmit the specific data by theuplink and downlink channels. The table below are thedetails for the performance of this chip. In the Equalizermode, where the retiming circuit and phase shifter areo ff to save the power, the total power consumption is79 mW. In the retiming mode, the power consumptionincreases to 105 mW but ISI jitter is further suppressed.GBCR2 was submitted in November 2019 and will betested in 2020.
4. Summary
In this paper, we present two prototypes of atransceiver ASIC, GBCR1 and GBCR2, in a 65-nmCMOS technology for the ATLAS ITk detector read-out upgrade. GBCR1 has been tested and GBCR2 issubmitted but not tested yet.The uplink channel of GBCR1, which operates at5.12 Gbps, recovers the data through a 6 meter AWG34Twinax cable. The ISI jitter is 79.9 ps when the CDRis o ff and the jitter decreases to 35.5 ps when the CDRis on. The downlink transmits the 2.56 Gbps data fromlpGBT well in the test. The total power consumption ofGBCR1 is 192 mW. The chip survives the total ionizingdose of 200 kGy with a gamma source.We redesigned the equalizer in the GBCR2 to adaptto the new readout baseline. By using an external clockwith a shared phase-shifter instead of a CDR for eachchannel for the re-timing, the power consumption of6 able 1: The jitter performance of GBCR2 Mode Input Jitter from RD53 (ps) Jitter from cable + GBCR (ps) Estimated Output jitter tolpGBT (ps)Uplink channel Rx Equalizer mode 100 81 181Rx Retiming mode 11 80The jitter of downlink output is 156.9 ps. each channel is kept to 105 mW. The output signal jit-ter is to 70 ps, which meets the requirement of the eRxin lpGBT. The downlink channel is optimized for 160Mbps data rate and suppresses the ISI jitter for the trans-mission in the cables. We expect to test GBCR2 soon.
Acknowledgments
This work was supported by the US-ATLAS phase-2upgrade grant administrated by the US-ATLAS phase-2 upgrade project o ffi ce and the O ffi ce of High EnergyPhysics of the U.S. Department of Energy under con-tract DE-AC02-05CH11231. The authors would like tobe grateful to Andrew Young and Dong Su from SLAC,Maurice Garcia-Sciveres and Veronica Wallangen fromLBNL, James Kierstead from BNL for their kind helpon the test of GBCR1. BibliographyReferences [1] ATLAS Collaboration, Technical Design Report for the AT-LAS Inner Tracker Pixel Detector, CERN-LHCC-2017-021 andATLAS-TDR-030, June 15 2018.[2] G. Aad et al., ATLAS pixel detector electronics and sensors,2008 JINST 3 P07007.[3] J. Troska et al., The VTRx + , an Optical Link Module forData Transmission at HL-LHC, in Proceedings of 2017 Topi-cal Workshop on Electronics for Particle Physics, Santa Cruz,CA, USA, September 11-15, 2017, PoS (TEPPP-17) 048.[4] C. Sos et al., Versatile Link PLUS transceiver development,2017 JINST 12 C03068.[5] Y. You, D. Huang, J. Chen, and S. Chakraborty, A 12GHz 67%Tuning Range 0.37ps RJrms PLL with LC-VCO TemperatureCompensation Scheme in 130nm CMOS, presented IEEE Ra-dio Frequency Integrated Circuit Symposium (RFIC), Tampa,Florida, June 1-3, 2014.[6] J. Prinzie et al., A 2.56-GHz SEU Radiation Hard LC-TankVCO for High-Speed Communication Links in 65-nm CMOSTechnology, IEEE T. Nuclear Science 65 (2018) 407-412.[7] S. Gondi and B. Razavi, Equalization and Clock and Data Re-covery Techniques for 10-Gb / s CMOS Serial-Link Receivers,IEEE J. Solid-State Circuits 76 (2007) 1999-2011.[8] C. H. Lee, M. T. Musta a, and K. H. Chan, Comparison of re-ceiver equalization using rst-order and second-order continuous-time linear equalizer in 45 nm process technology, in Proceed-ings of International Conference on Intelligent and AdvancedSystems, pp. 795C800, Kuala Lumpur, Malaysia, July 2012.[9] J. Prinzie et al., A Low Noise Fault Tolerant Radiation Hardened2.56 Gbps Clock-Data Recovery Circuit With High Speed FeedForward Correction in 65 nm CMOS, 2019 IEEE 10th LatinAmerican Symposium on Circuits & Systems (LASCAS) [10] P. Moreira et al., The lpGBT: a radiation tolerant ASIC forData, Timing, Trigger and Control Applications in HL-LHC,Presented at the Topical Workshop on Electronics for ParticlePhysics (2019), Santiago de Compostela, Spain, September 3,2019.[11] T. Liu. A 4.9-GHz low power, low jitter, LC phase locked loop,2010 JINST 5 C12045.[12] A. Tsuchiya et al., Low-Power Design of CML Drivers for On-Chip Transmission-Lines, in Proceedings Workshop on Synthe-sis and System Integration of Mixed Information Tech. April2006.[13] L.P. Baskaran et al., Technique for transmitter preemphasis andreceiver equalization in a high-speed backplane environment,Consumer Electronics, ICCE Digest of Technical Papers, pp.373C374, Jan. 2006[14] F. Arteche Gonzalez et al., Extension of RD53, CERN-LHCC-2018-028; LHCC-SR-008, September 7, 2018.[15] Szymon Kulis et al., A High-resolution, Wide-range, Radiation-hard Clock Phase-shifter in a 65 nm CMOS Technology, Pro-ceedings of the 26th International Conference ”Mixed Designof Integrated Circuits and Systems” June 27-29, 2019, Rzeszw,Poland[16] D. Yang S. Kulis D. Gong J. Ye P. Moreira J. Wang ”A High-Resolution Clock Phase-Shifter in a 65 nm CMOS Technology”Proceedings of International Conference on Technology and In-strumentation in Particle Physics 2017 vol. 212 2017s CMOS Serial-Link Receivers,IEEE J. Solid-State Circuits 76 (2007) 1999-2011.[8] C. H. Lee, M. T. Musta a, and K. H. Chan, Comparison of re-ceiver equalization using rst-order and second-order continuous-time linear equalizer in 45 nm process technology, in Proceed-ings of International Conference on Intelligent and AdvancedSystems, pp. 795C800, Kuala Lumpur, Malaysia, July 2012.[9] J. Prinzie et al., A Low Noise Fault Tolerant Radiation Hardened2.56 Gbps Clock-Data Recovery Circuit With High Speed FeedForward Correction in 65 nm CMOS, 2019 IEEE 10th LatinAmerican Symposium on Circuits & Systems (LASCAS) [10] P. Moreira et al., The lpGBT: a radiation tolerant ASIC forData, Timing, Trigger and Control Applications in HL-LHC,Presented at the Topical Workshop on Electronics for ParticlePhysics (2019), Santiago de Compostela, Spain, September 3,2019.[11] T. Liu. A 4.9-GHz low power, low jitter, LC phase locked loop,2010 JINST 5 C12045.[12] A. Tsuchiya et al., Low-Power Design of CML Drivers for On-Chip Transmission-Lines, in Proceedings Workshop on Synthe-sis and System Integration of Mixed Information Tech. April2006.[13] L.P. Baskaran et al., Technique for transmitter preemphasis andreceiver equalization in a high-speed backplane environment,Consumer Electronics, ICCE Digest of Technical Papers, pp.373C374, Jan. 2006[14] F. Arteche Gonzalez et al., Extension of RD53, CERN-LHCC-2018-028; LHCC-SR-008, September 7, 2018.[15] Szymon Kulis et al., A High-resolution, Wide-range, Radiation-hard Clock Phase-shifter in a 65 nm CMOS Technology, Pro-ceedings of the 26th International Conference ”Mixed Designof Integrated Circuits and Systems” June 27-29, 2019, Rzeszw,Poland[16] D. Yang S. Kulis D. Gong J. Ye P. Moreira J. Wang ”A High-Resolution Clock Phase-Shifter in a 65 nm CMOS Technology”Proceedings of International Conference on Technology and In-strumentation in Particle Physics 2017 vol. 212 2017