200 mm Sensor Development Using Bonded Wafers
M. Alyari, R. Bradford, M. Campanella, P. Camporeale, R. Demina, J. Everts, Z. Gecse, R. Halenza, U. Heintz, S. Holland, S. Hong, S. Korjenevski, A. Lampis, R. Lipton, R. Patti, J. Segal, K.W. Shin
PPrepared for submission to JINST
200 mm Sensor Development Using Bonded Wafers
M. Alyari b R. Bradford a M. Campanella b P. Camporeale b R. Demina e J. Everts b Z. Gecse b R.Halenza b U. Heintz g S. Holland c S. Hong f S. Korjenevski e A. Lampis b R. Lipton b R. Patti f J.Segal d K.W. Shin a a Argonne National Laboratory, Lemont, Illinois 60439 b Fermilab, P.O. Box 500, Batavia, Illinois USA c Lawrence Berkeley National Laboratory (LBNL),Berkeley, CA USA d SLAC National Accelerator Laboratory, Menlo Park, Ca USA e University of Rochester, Rochester, NY USA f NHanced Semiconductors, Naperville, IL USA g Brown University, Providence, RI USA
E-mail: [email protected]
Abstract: Sensors fabricated from high resistivity, float zone, silicon material have been the basisof vertex detectors and trackers for the last 30 years. The areas of these devices have increased froma few square cm to 200 m for the existing CMS tracker. High Luminosity Large Hadron Collider(HL-LHC), CMS and ATLAS tracker upgrades will each require more than 200 m of silicon andthe CMS High Granularity Calorimeter (HGCAL) will require more than 600 m . The cost andcomplexity of assembly of these devices is related to the area of each module, which in turn is set bythe size of the silicon sensors. In addition to large area, the devices must be radiation hard, whichrequires the use of sensors thinned to 200 microns or less. The combination of wafer thinningand large wafer diameter is a significant technical challenge, and is the subject of this work. Wedescribe work on development of thin sensors on 200 mm wafers using wafer bonding technology.Results of development runs with float zone, Silicon-on-Insulator and Silicon-Silicon bonded wafertechnologies are reported. a r X i v : . [ phy s i c s . i n s - d e t ] S e p ontents Particle Physics collider experiments are increasingly dependent on silicon diode detectors fortracking, vertexing, and calorimetry. These detectors can provide precise position and energy infor-mation and are sufficiently radiation hard for the challenging environment of the High LuminosityLHC. ATLAS[2] and CMS[6] trackers at HL-LHC plan silicon tracking systems of ≈ m each.The CMS high granularity calorimeter[5] plans a detector of 600 m area tiled with planes of sensorsdiced from 8" wafers. In addition silicon-based sensors are increasingly utilized for x-ray imagingand other applications that will require large areas of sensors. Modern technologies such as 3-Dintegration often can only be affordably implemented on larger wafers. These needs motivate thedevelopment of technologies to move sensor wafer fabrication from 6" to 8" wafers [4].Sensors for high energy physics must have thin (100-300 micron) active regions for radiationresistance and low mass. Typical 200 mm wafer processing equipment requires thicker (775 micron)material for automated handling and to limit breakage. These thick wafers must be thinned aftertopside processing to the 100-300 microns needed for HEP detectors. Good sensor performancewith low leakage current requires a high quality backside contact. This requires a p+ or n+ implantand associated annealing, metalization, and sintering. The standard high temperature annealingprocess precludes the presence of topside metalization before the anneal. There are several possibleprocess solutions to this: – 1 – The topside can be completely patterned and oven-annealed, topside metalization deposited.The wafer is then thinned, implanted and annealed using a laser that locally melts the backsideimplanted region[11].• The wafer can be implanted on front side, thinned, implanted on the back side, annealed, andmetal deposited and patterned on the front side. This involves handling and patterning a thinwafer during the final steps.• Use of alternative low temperature annealing processes such as microwave annealing[8][7].• The sensor (float zone) wafer backside can be implanted, polished, then Silicon-on-Insulator(SOI) bonded to a handle wafer for processing. The top (device) wafer is then thinned to therequired thickness and polished. After the topside process is complete the backside handleand oxide are removed and an aluminum backside contact electrode is deposited.• The sensor wafer can be Silicon-Silicon (SiSi) bonded to a low resistivity handle wafer ofthe same type. The topside can be thinned to the appropriate thickness, polished and fullyprocessed. The resulting stack can then be thinned to the required physical thickness. Nobackside processing other than metalization is necessary.We have chosen to explore the last two technologies as part of a US Small Business InnovativeResearch (SBIR)-funded development project aimed at production of large area, thinned, radiationhard silicon detector systems. The initial runs used the Novati foundry in Austin, Texas and thefinal run used the NHanced foundry in Morrisville, North Carolina. This development was guided by the need for radiation hard detectors for Particle Physics. Designsare driven by radiation induced effects, including the increase of acceptor levels, which require anincrease in operating voltage, and the increase in leakage current[12]. These effects can be mitigatedby making the detectors thin and operating them at low temperature. The detectors planned for HL-LHC trackers are based on n-on-p diodes, thinned to a volume compatible with acceptable signalto noise after irradiation [14]. At the end-of-life the devices also must withstand bias voltages up to1000 volts. The CMS HGCAL application required only DC-coupled pad sensors. Tracker sensorsincorporate AC coupling capacitors and polysilicon bias resistors on the microstrip sensors.Run Substrate Active/PhysicalThickness ( µ m ) Process Splits Date1 FZ 725,500/725,500 DC p-stop, oxide 4/20152 SOI, FZ 200,500/700,500 DC p-stop, oxide 3/20163 SOI 275/275 AC p-stop,n+ 11/20174 SiSi 200/700 DC p-stop 3/2019 Table 1 . Summary of process runs, substrates used and process splits. Oxide splits used either wet or dryoxydation. P-stop splits varied the p-stop doping – 2 –
Process Development
The fabrication process is based on processes developed at SLAC and LBNL[10]. These processeswere adapted for the foundry process at NHanced. The process steps, including implantationand annealing were modeled using Silvaco tools[13] at Fermilab. In total there were four runs,summarized in Table 1. The first run used bulk float zone wafers to establish the overall process.Runs 2 and 3 used SOI stacked wafers and the last used SiSi wafer stacks. Initial developmentruns were DC-coupled diodes processed using full thickness wafers. For the float zone wafers theminimum final thickness was 500 microns due to the fragility of thinner wafers. The initial runswere used to understand leakage current and breakdown characteristics, explore guard ring variants,and explore process splits such as p-stop dose and wet or dry oxidation. These also helped to informthe development of design rules for subsequent fabrications. The third run added AC coupling andpolysilicon resistors.The overall process flow for DC and AC coupled variants is given in table 2. An initialsacrificial oxide is grown to getter out impurities. Combined p-spray and p-stop isolation was usedin the first run, and p-stops in the other runs. Another sacrificial oxide layer is used to provide themask for all of the topside implants, providing good relative registration. The specific p, p+, or nimplants are then defined by photoresist. The AC process includes steps to define the polysiliconresistors and coupling capacitors. The relative alignment of the mask layers is better than 3 microns.Figure 1 shows the result of a process simulation of the full AC/polysilicon process. stripimplant biasimplantoxideAluminumPolysilicon resistorAC couplingcapacitor contactp-stops
Figure 1 . Results of a simulation of the full AC wafer fabrication process with the corresponding structureson a typical silicon strip detector.
The SOI runs were fabricated with a 200 or 250 micron thick float zone device layer bonded toa 500 micron thick handle layer with ≈ SiO • • Oxide openings define n+ and pPattern and implant top • • n+, p-stop, p-edgeanneal • • Remove implant oxideGrow final oxide • •Dep/pattern/etch polysilicon •Pattern/etch Capacitor Oxide • Remove oxide for AC couplingDep/pattern/etch capacitor • SiO − SiN − SiO dielectricPattern/etch contacts • Bias and resistor contactsDep/pattern/etch aluminum • • Top metalDep/pattern/etch passivation • • Top SiO Bond to top handle • Thinned SOI processRemove back handle, etch BOX • Thinned SOI processDeposit backside Al , remove handle • Thinned SOI process Table 2 . Summary of process flows for DC and AC runs biased from the topside contacts. Topside contacts are acceptable for applications with moderateradiation requirements. At high radiation exposures the resistivity of the topside contact increasesand may make topside bias connections problematic[3]. In run 3 a topside handle was attached,the backside handle wafer was removed, and the SOI buried oxide (BOX) was etched away. Thebackside was then metalized. In both cases standard float zone wafers were processed in parallel ascontrol samples.The last run used a Silicon-Silicon (SiSi) bonded substrate. This consists of a high resistivitywafer directly bonded to a low resistivity handle such that the interface is transparent to chargecarriers. This construction has the advantage that the ohmic backside contact is built-in as part ofthe bonded wafer interface. It eliminates the pre-bonding backside implant step and the post processbackside handle removal and BOX etch steps needed for the SOI devices. The wafer simply needsto be ground down to the desired physical thickness and aluminized. Silicon-Silicon bonding is,however, a less well-established and controlled process.Full investigation of the SiSi process was interrupted by the sale of the Novati foundry whereRuns 1-3 were fabricated. This required re-qualification of the process at the NHanced foundry inNorth Carolina. The initial NHanced run (Run 4) had poor oxide quality and large leakage currents.Therefore we were not able to fully qualify the SiSi process within the constraints of the R&Dprogram. – 4 –
Sensor and Test Structure Designs
A 200 mm wafer provides ample space for both test structures and prototype designs. For Runs2 and 3 we included a variety of designs from the High Energy Physics (HEP) and Basic EnergySciences (BES) communities. These included strip and pixel detectors for HEP and pixel sensorsfor x-ray imaging. We also included a variety of test structures including pad diodes with guard ringvariants, MOS test structures, and resistor and capacitor structures in the AC run. Figure 2 showsthe overall layout of the wafers. Full size ( ≈ × cm ) strip and macro-pixel sensors intended asprototypes for the CMS inner tracker pixel-strip (PS) module were included in runs 2 and 3. Run 4was dedicated to a prototype full-wafer CMS High Granularity Calorimeter design. Figure 2 . Layouts for the three bonded wafer submissions.
Here we consider only the devices from Runs 2-4, which incorporated wafer bonding technologies.The primary characterization tools were test structure diodes of ≈ cm . Samples of these diodeswere VI and CV tested for several wafers in each run. Test structure diodes were IV tested to 600or 800 V. Test structures with currents exceeding 10 µ A were considered to be in breakdown. Wefound substantial variations in breakdown voltage within a wafer, especially in Run 2. This made itdifficult to establish statistically significant optimum values for the various process splits.
Run 2 consisted of SOI wafers with the backside handle wafer intact. The sensors on these wafershad to be biased from the topside contact since the backside implant is not accessible. Diode CVtests showed a full depletion voltage of 60 ±
10 Volts (figure 3). The measured active thickness is200 microns. The calculated effective doping concentration is 2 . ± . × / cm .The leakage current at full depletion ranged from 0.5 to 0.75 µ A / cm . The range of breakdownvoltage varied considerably from diode to diode within a wafer (figure 4). The devices processedwith dry oxidation and p-stop implant dose of 5 × had the best overall performance. In addition,some devices were observed to have hysteresis in the breakdown voltage, with the breakdown usuallydecreasing in subsequent iterations of the test. Devices with the single guard ring design generallyhad higher breakdown voltages by ≈
100 Volts with respect to the multi-guard designs tested.– 5 –
50 100 150 200 250 300- Bias Voltage0100020003000400050006000700080009000 · / C ^ Diode CV
Run 2 (SOI)Run 3 (SOI)Run 4 (SiSi)
Figure 3 . 1 / C vs V bias of Run 2, 3 and 4 test diodes. These are typical of diodes in each run. Run 3 wafers were physically thinned and measured to have an active thickness of 250 µ m . Thesedepleted at 170 ±
15 Volts, giving an effective doping concentration of 3 . ± . × / cm .The average leakage current at full depletion ranged from 0.18 to 0.3 µ A / cm , considerably betterthan the Run 2 structures. In general the breakdown voltage for these devices was higher and moreuniform than the Run 2 sensors (figure 4) and did not show hysteresis. We did not see a clearsystematic difference between the various n-implant and p-stop process splits. Run 4 wafers were fabricated as a stack of low and high resistivity silicon. The high resistivity activeregion was measured to be 200 microns thick. Depletion voltage for these sensors was 60 ±
10 Volts(figure 3). The calculated doping concentration for the float zone layer is 2 . ± . × / cm .The leakage current is shown in figure 4c. It is around 10 µ A / cm at 20V above depletion, roughlya factor of 10 higher than the SOI devices. The test diodes also show a rapid increase in currentat 100-150 V, increasing to 0.1 mA at 500 V. The increase does not have the extremely sharp risecharacteristic of avalanche breakdown. This may be due to fields penetrating into the low resistivitywafer and the bond interface, drawing current from defects in these regions. A pre-bonding p+implant in the float zone wafer could reduce this issue, but would also make the process morecomplex. Metal Oxide Semiconductor (MOS) test structure CV measurements are shown in figure 5. Thesemeasurements provide indications of the overall surface quality, including oxide and interfacecharges. The first three runs show distinct patterns. The first and third run show abrupt transitions– 6 –
100 200 300 400 500 600 700 800- Bias Voltage00.010.020.030.040.050.060.070.080.090.1 - · C u rr en t ( A m p s ) Wet, 5x10 Dry, 5x10 Dry, 5x10 Dry, 5x10 - · C u rr en t ( A m p s ) B-5x10 P-1x10 B-5x10 P-1x10 B-8x10 P-1x10 B-8x10 P-1x10 - · C u rr en t ( A m p s ) Figure 4 . One cm test diode current vs voltage characteristics for diodes with a single guard ring for wafersfrom Runs 2 (SOI, top), 3 (SOI, middle) and 4 (SiSi, bottom). Note the compressed scale on the SiSi VI plot. between depletion and accumulation regions, indicating good interface quality. The small slope inthe Run 2 CV curve is indicative of problems in the bulk-oxide interface. Run 1 had a large 6 Voltflatband voltage, indicating significant oxide charge density. This was improved for Run 3, with a2.7 Volt flatband voltage corresponding to an oxide charge density of 1 . × / cm . The MOSstructures for the wafers in Run 4 did not show a clear distinction between the accumulation anddepletion regions in the MOS test structures. Therefore the oxide charge could not be determined.This is true for both the Si-Si devices and float-zone controls. This is an indication of a poor siliconbulk to oxide surface interface. Run 3 included polysilicon bias resistors and AC coupling capacitors. The polysilicon structureswere implanted with a nominal phosphorous dose of 1 × / cm . The resistance of the polysiliconresistors ranged from 750 to 1000 Ohms per square. Serpentine resistors on the CMS PS-s sensorsmeasured 207 ± × Ω , at the low end of the acceptable range for sensors of this type. ACcoupling capacitors were designed with both oxide and nitride layers. For these devices the relevantquantitiy is capacitance per unit lenght. These capacitors were measured to have a capacitance of– 7 – .40.60.81 Run 1 MOS CV C / C ( m a x ) Run 2 MOS CV − − − − Run 3 MOS CV
CCmax
Bias Voltage
Figure 5 . MOS CV curves for Run 1,2 and 3 test structures. Capacitance values are scaled to the maximumvalue for each structure. Note the small range for the Run 2 structure. Run 4 structures did not yield ameaningful CV curve. . ± . ≈
20 pF/cm, indicating a thin oxide/nitridedielectric. − × C u rr en t ( A m p s ) NHanced 12E14 n/cm^2 VI
T=-10 Deg CT=-20 Deg CT=-30 Deg C (a) O v e r f l o w s -10 Deg C-20 Deg C-30 Deg CNHanced 1.2E15 Laser Off Overflows (b) Figure 6 . a) Current as a function of bias and temperature for an irradiated SOI HGCAL sensor. All curvesshow a break at about 300 V. b)Number of events with signal beyond 3 σ of the pedestal for various sensortemperatures for the HGCAL sensor in a. There is a rapid increase in noise in the same region – 8 –
100 200 300 400 500 600 700 800- Bias Voltage0510152025 S i gna l -10 Deg C-20 Deg C-30 Deg C NHanced 7.5E14 Laser
Figure 7 . Laser signal as a function of voltage for three values of detector temperature.
A Run 3 HGC half-sensor was included in an neutron irradiation run at the RINSC reactor inRhode Island. This run had an estimated 1 MeV neutron equivalent fluence of 1 . × n / cm . Inaddition to the usual VI tests these devices were tested for charge collection with a 1064 nm laserand transimpedance amplifier. An 200 mm semi-automatic probe station equipped with a thermalchuck was used. A seven pin probe card provided contact to the central pad of the hexagonal arraywhile maintaining ground potential in the six surrounding pads. Non-Gaussian noise is measuredby counting events beyond 3 σ of the pedestal. This is an indication of possible breakdown.Voltage-current curves for the irradiated Run 3 sensor are shown in Figure 6a. The currentratios are consistent with the standard temperature dependence of leakage current. Figure 6b showsthe number of non-Gaussian noise events in runs with the laser off. There is a increase in noise inthe region between 200 and 300V. We note that this corresponds to a break in the leakage currentVI curves in that region. We conclude that there is a possible onset of breakdown in this region.Laser test charge collection results for the Run 3 sensor are shown in figure 7. We believethat the variation in charge collected with temperature is due to the temperature variation of theabsorption coefficient for infrared light at this wavelength[9][1]. The charge collection appears toplateau at 600-700 Volts. The calculated in depletion voltage is ≈
750 V for this fluence, includingan estimate of the annealing in the reactor during exposure.
We have demonstrated the fabrication of 8" sensors with thin active regions using both SOI andSiSi bonded wafers. SOI bonded wafers with the handle wafers removed (Run 3), provided the bestresults, with acceptable leakage currents and breakdown voltage values and consistency. This runalso demonstrated AC coupling resistors and capacitors with acceptable characteristics. A sampleof Run 3 sensors were irradiated to 1 . × n / cm . These showed the expected leakage currentand depletion characteristics. Evidence was found for a non-Gaussian component of the noise above300 Volts. We were unable to qualify the Si-Si process in these studies due to changes in fab site– 9 –nd processing. The SOI process worked well and shows promise for future development of sensorswith thin active layers. This manuscript has been authored by Fermi Research Alliance, LLC under Contract No. DE-AC02-07CH11359 with the U.S. Department of Energy, Office of Science, Office of High EnergyPhysics. Partial funding for this work was provided by the DOE Small Business Innovative Research(SBIR) programWe would like to thank the summer students (P. Camporeale, J. Everts, R. Halenza, and A.Lampis) who participated in making measurements of the sensors and test structures.
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