# Compact gate-based read-out of multiplexed quantum devices with a cryogenic CMOS active inductor

L. Le Guevel, G. Billiot, S. De Franceschi, A. Morel, X. Jehl, A.G.M. Jansen, G. Pillonnet

aa r X i v : . [ qu a n t - ph ] F e b Compact gate-based read-out of multiplexed quantum devices with acryogenic CMOS active inductor

L. Le Guevel,

1, 2, a) G. Billiot, S. De Franceschi, A. Morel, X. Jehl, A.G.M. Jansen, and G. Pillonnet Univ. Grenoble Alpes, CEA, LETI, F-38000 Grenoble, France Univ. Grenoble Alpes, CEA, Grenoble INP, IRIG, PHELIQS, F-38000 Grenoble, France (Dated: February 10, 2021)

In the strive for scalable quantum processors, signiﬁcant effort is being devoted to the development of cryogenic clas-sical hardware for the control and readout of a growing number of qubits. Here we report on a cryogenic circuitincorporating a CMOS-based active inductor enabling fast impedance measurements with a sensitivity of 10 aF and aninput-referred noise of 3.7 aF/sqrt(Hz). This type of circuit is especially conceived for the readout of semiconductorspin qubits. As opposed to commonly used schemes based on dispersive rf reﬂectometry, which require mm-scalepassive inductors, it allows for a markedly reduced footprint (50µm × 60µm), facilitating its integration in a scalablequantum-classical architecture. In addition, its active inductor results in a resonant circuit with tunable frequency andquality factor, enabling the optimization of readout sensitivity.An ingenious use of the laws of quantum mechanics has ledto a new computing paradigm, generally known as quantumcomputing, that promises exponential speed-up in the solutionof certain types of problems . Using a prototypical quantumprocessor with 53 operational superconducting quantum bits(qubits), a ground-breaking experiment was recently able toperform a ﬁrst experiment towards quantum supremacy , trig-gering more extensive research on such a goal . Practical im-plementations of quantum computing, however, are expectedto require much larger numbers of physical qubits .Solid-state implementations seem to offer the best scalabil-ity prospects. While superconducting qubits are currently theleading platform, semiconductor spin qubits are emerging as aserious contender owing to the possibility to leverage the inte-gration capabilities of silicon technology . In both cases, thequantum processor can only function at very low temperature,typically below 0.1 K (only recently, it was shown that siliconqubits could be operated even above 1 K with limited loss ofﬁdelity ).In a scale-up prospect toward increasingly large numbersof qubits, the introduction of classical cryogenic electron-ics positioned as close as possible to the qubits is widelyconsidered as a necessity. Various solutions have been pro-posed and partly demonstrated to a ﬁrst proof-of-conceptlevel. These include low-temperature (de)multiplexers ,analog-to-digital and digital-to-analog converters , low-noise ampliﬁers , RF oscillators , transimpedanceampliﬁers , and digital processors . In a DRAM-likestrategy , these cryogenic components can signiﬁcantly re-duce the number of electrical lines running through the hostcryostat, thereby limiting the associated heat load and increas-ing interconnect reliability. A CMOS-based cryogenic con-troller operating at 3K was recently reported enabling high-ﬁdelity operations on an electron-spin two-qubit system . Asfar as qubit readout is concerned, however, relatively little hasbeen done. Measuring the qubit state requires detecting smallvariations in the impedance of an LC tank circuit coupled to a) Electronic mail: [email protected] the qubit, which is commonly done through rf reﬂectome-try. The inductive element of this tank circuit consists of asurface-mount inductor or a microfabricated superconductingcoil. Even for this second case, the corresponding footprintis relatively large ( ∼ mm ) and hence hardly compatible withlarge-scale qubit integration.Here we propose an alternative readout technique involv-ing a cryogenic CMOS-based active inductor with a compactdesign. Besides its reduced footprint favoring scalability, thisCMOS inductor offers the possibility to tune the characteris-tic frequency and the quality factor of the resonator, which isinstrumental in optimizing measurement sensitivity. As op-posed to conventional reﬂectometry, our method consists inmeasuring the tank impedance at resonance. The cryogenicread-out circuit is composed of a current source exciting theLC tank, an ampliﬁer to read the voltage response, and a mul-tiplexed capacitor bank to select different devices under test(DUT). We characterized the circuit sensitivity and tunabilityat 4.2 K demonstrating its capability to measure capacitancesas low as 10 aF. By applying our technique to a gate-coupledMOSFET co-integrated on the same chip we reveal typicalsignatures of quantized electronic states. I. IMPEDANCEMETRY

Capacitive spectroscopy of gate-controlled quantum-dotdevices allows the detection of electronic quantum stateswithin the structure, including the ﬁrstly occupied electronstates. For enhanced detection sensitivity at high speed, thegate capacitance of the device under test (DUT), representedas a single-electron transistor in Figure 1b, is connected to aninductance to form an LC resonator. In a gate-coupled read-out scheme of the quantum state, the response of the tank atcryogenic temperature excited near resonance frequency f r isconveyed back to room temperature for probing and analysis,usually with homodyne I-Q detection. The phase of the tankresponse becomes an image of the change in DUT capacitance ∆ C ≪ C p (see Figure 1a) through the relation ∆φ = Q ∆ C / C p around f r with Q the resonator quality factor and C p the par-allel capacitance. (cid:0)✁✂ (cid:0) ✁✂✄☎✄✆✝✞✟✠✡✟☛☞✟✌✠✍✎ ✏✑✒✓✔✕✖✔✕✗✘✙✚✒✛✙✜✒✢✑✢✘✚✙✣✜✙✜✢✑✘✑✗✗✜✤✜✗✑✘✜✒✗✕✥ ✄ ✦✧★✩ ✦✪✝✝ ✦ ✟☛☞✫✫ ✬✭✭✟✠✡ ✮✭✭✟✠✡ ✟✠✡(cid:0)✠✡✯✰✱✟✠✡✆✝✞✲✳ ✲✳ ✟✌✠✍✎✴ ✵ ✵✶✷✸✷✹✺✻✼✷✺✽✾✿❀ ❁❂❃ ❄❄ ❅❅❅❆ ❅❆❇❃ ❄❄❇❈ ❉✼❊✷❋●❍✹✷✼✷✺✽✾✿❀ ❁❂ ❅❅❇■ ❄❄❇■ ❄❄ Figure 1.

Integration of measuring circuitry for scalable read-out of quantum capacitance. a , Schematic signals of the complexscattering coefﬁcient S and impedance Z of a resonant circuitin, respectively, reﬂectometry and impedancemetry. b , Compari-son between a typical reﬂectometry setup (left) and the proposedimpedancemetry setup (right) for the measurement of the quantumcapacitance C q of a single-electron transistor. Impedancemetry lever-ages cryogenic electronics to achieve higher integration of the mea-surement circuitry by getting rid of bulky directional couplers. Red(respectively green) arrows represent voltages (resp. currents). Red-green arrows emphasize the voltage-current interdependence due tosignal propagation in 50 Ω lines. Figure 1b shows a schematic comparison for resonance ex-periments between the commonly used method of reﬂectom-etry and the here employed method of impedancemetry. Re-ﬂectometry uses voltages to excite and probe the resonator viathe scattering or transmission parameters , based on prop-agating waves. To isolate the incoming and outgoing signals,directional couplers or circulators are used.Impedancemetry uses currents to excite and probe the res-onator via the impedance parameters without the need ofbulky coupling elements. The incoming signal V in at the res-onant frequency f r , generated at room temperature, is con-verted in a current I in = G m V in with a voltage-controlled cur-rent source of transimpedance G m at the base-temperaturestage. The input current I in creates a voltage V out = Z r I in through the tank impedance Z r that carries the informationabout the DUT capacitance. V out is conveyed to a low-powerunity-gain ampliﬁer (follower) placed nearby the DUT to re- duce parasitic capacitance C par . Main ampliﬁcation is placedat a higher temperature (typically 4 . Ω impedance matching plays no role in the optimiza-tion of the resonant circuit depending on the inductor andthe parasitic capacitors. However, the cryogenic circuitry re-quired by impedancemetry generates extra noise compared toreﬂectometry, which needs to be minimized. The impedanceof the resonator naturally ﬁlters out-of-resonance components(see Figure 1a) such as low-frequency ﬂicker noise from elec-tronics. In the perspective of quantum computing involving aqubit matrix, V in could contain a comb of excitation frequen-cies to excite a set of frequency-selective resonators (see Sup-plementary Material I with an estimation of the scaling forlarge qubit arrays).In the case of impedancemetry, without the need of direc-tional couplers, the footprint of the read-out circuitry is re-duced. Using modern CMOS technologies with sub-100nmnodes, the additional circuitry of current sources and follow-ers easily ﬁts on a chip with size comparable to the hundredsof qubits chip (

The active inductance behavior is realized by transforminga capacitor C L into an inductance L = C L / G m , G m , via twotransistor devices of transimpedance G m , and G m , forming agyrator . The non-ideal ﬁnite conductance and parasitic ca-pacitance of the transistors set the resonant frequency f r andquality factor Q . More advanced active inductance architec-tures incorporate a negative resistor in parallel to the induc-tance in order to improve Q up to a few hundred with inde-pendent tuning of the inductance value L and the quality factor Q .Fine calibration of the tunable inductance value using vari-able capacitors leads to a precise deﬁnition of the resonantfrequency value, ideal for optimal frequency-multiplexing oflarge qubit matrices. The tunability of the Q -factor enablesdifferent modes of read-out. High- Q gives a precise mea-surement of quantum capacitance to calibrate qubit matrices.Lower- Q is more suitable for fast read-out during quantumcomputation. III. INTEGRATED CIRCUIT DESIGN

The impedancemetry experiment was integrated on a sin-gle chip with multiplexed quantum devices using the Fully-Depleted Silicon-On-Insulator (FD-SOI) 28nm CMOS tech-nology. The FD-SOI technology is very well suited for high-speed cryogenic applications with lower variability thanbulk technologies , less sensitivity to carrier freeze-out, andthreshold-voltage tuning with the use of the back-gate . Theintegration of classical circuitry with small-enough transistorsthat exhibit quantum properties is a plus to validate efﬁcientlynew circuit architectures The realized integrated circuit contains the current source,the active inductance with addressable capacitor banks fortunability, the multiplexed DUTs, and the ampliﬁcation stage(Figure 2a, b). During design, we focused on bringing downthe footprint and power consumption of the active inductancebeing the main original component of our circuit. The com-plete ampliﬁcation and current generation was added on-chipto facilitate testing the concept of impedancemetry at 4 . . The evolution of transistor characteristics towardsthe lowest temperatures was extrapolated from the tempera-ture variation in foundry models but also from acquired 4 . .The active inductance follows a known NMOS-basedKarsilayan-Schaumann architecture . The gyrator is madeof a single-ended negative transconductance − G m , and adifferential transconductance stage G m , . The gyrator trans-forms a tunable capacitance C L into an inductance L ( C L ) = C L / G m , G m , . An added metal-oxide-metal (MOM) capaci-tor C p of 136 fF parallel to L controls the resonant frequency f r = / π p L ( C L ) C p . No dependence in temperature is ex-pected for MOM capacitors . Adding C p makes the measur-ing circuit less sensitive to the DUT-capacitance with the in-creased tank capacitance but avoids the inﬂuence of unknownparasitic capacitances at cryogenic temperatures (e.g. sub-strate parasitics). Hence, the resonant frequency f r is set by C p , C L , and G m , i = , . C L is implemented with one main metal-oxide-metal (MOM) capacitor of 362 fF in parallel with twodigitally-controlled binary-weighted MOM capacitors of 68and 136 fF (see Supplementary Material II). At room temper-ature, the emulated L ranges from 5.3 to 8 . f r from 128 to 165 MHz (see Supplementary Material III). Theestimated power consumption of the resonator is 85 µW andcorresponds to a footprint of 8 . / qubit assuming a 10 × C R at the foot of the differentialtransconductance stage allows to introduce a negative re-sistance in series with the active inductance, leading tohigher Q-factor with an increased parallel effective resistance R ( C R , C L ) . The Q -factor of the active inductance deﬁned as Q = R ( C L , C R ) p L ( C L ) / C p depends on C R and C L . By tuning C L , then C R , L and Q can be adjusted to any desired value apart from possible instabilities. To tune the Q factor, we choose tocover a wide range of C R values in steps of 23 fF by selecting4 binary-weighted MOM capacitors of 23, 46, 92, and 184 fF.From room-temperature simulations, these settings allow tocover a wide range of quality factors Q from 7 to 300, includ-ing the unstable states with negative Q (see SupplementaryMaterial III).The voltage-controlled current source exciting the resonatoris made of a current mirror combined to an RC bias tee. Thebias tee superimposes DC signals from the diode transistorto set the DC operating point of the current source and ACsignals from the excitation input V in to generate the AC cur-rent I in . The RC ﬁlter of the bias tee consists of R bt (polysili-con resistor of 10 M Ω ) and C bt (MOM capacitor of 406 fF) toreach a characteristic frequency of 39 kHz. As no large signals V in are required, the current source operates in subthresholdregime with a bias current of only 0 . G m of 3 . / mV and bandwidth of3 . V bias when selected. The differential transconductancestage of the active inductance copies the DC common-modevoltage V cm to the DUT gate potential, such that the DC gatevoltage V gs = V cm − V bias can be varied via V bias (see Figure 2).Once excited by I in , the tank voltage is ampliﬁed, then sentthrough a unit-gain buffer for detection at room temperaturevia meter-long cable. The ampliﬁer is a common-source N-type single-stage and the 1:1 buffer is a common-drain N-typesingle stage (see Figure 2a). Based on room-temperature sim-ulations, the ampliﬁer has a gain A of 15 dB and a bandwidthof 1 . . L modulates f r andgenerates phase noise in V out . The phase noise spectrum of V out around the carrier frequency f r extracted from room-temperature steady-state simulations (SST) exhibits a ﬂickercomponent (see Supplementary Material III) on time-scale>10 ms, induced by a noisy modulated L . For a typical Q of81 with sufﬁciently fast measurements to avoid 1 / f noise, weget a phase noise of 0 .

002 ° / √ Hz that gives an input-referrednoise of 3 . / √ Hz.Voltage excitation and homodyne detection are performedat room temperature with an all-digital lock-in ampliﬁer (Fig-ure 2c). Different conﬁgurations for single (I) and double

Figure 2.

Setup with on-chip electronics. a , On-chip circuit implementation of the active inductance (pink), current excitation (green),test capacitor bank (blue), and ampliﬁcation stage (red). For clarity, the bias MOSFETs operating in DC are drawn of smaller size thanMOSFETs in the high-frequency signal chain. b , Simpliﬁed view of the on-chip resonant circuit placed at 4 . c , Room-temperature homodyne detection with single (I) and double (II) demodulation of the circuit output V out and generation of voltage excitation V in at modulation frequencies f (150-200 MHz) and f (1 kHz). (II a,b) demodulation are further described in the followingsection when needed. IV. IMPEDANCEMETRY CIRCUIT CHARACTERIZATION

Without the assistance of low-temperature models, the op-erating point of the circuit had to be determined experimen-tally starting from room-temperature settings of bias voltagesand currents. The increase in threshold voltage of NMOS(resp. PMOS) transistors at 4 . . − V cm = .

48 V was obtainedwhile monitoring the tank impedance via repeated frequencysweeps until a typical resonance behavior up to 200 MHzemerges for the lowest values of C L and C R . The gain of thelow-temperature ampliﬁcation stage at f r is optimized withrespect to the curent bias of ampliﬁer and buffer (see Supple-mentary Material IV). The main results of the impedanceme-try with respect to tunability and detection sensitivity areshown in Figure 3.The amplitude and phase of V out using single homodyne de-tection (I) without any connected DUT are shown in Figure 3afor the 4 C L values from 362 to 566 fF and two C R values cho-sen between 0 and 322 fF depending on C L . V out at maximalamplitude was kept equal to 1 . V in to avoidnon-linearities coming from non-linear MOSFETs behavior.The resonance frequency f r varies by 5 . . C L . The quality factors Q extracted froma linear ﬁt of the phase around f r are shown in Figure 3b. The Q values range from 80 to 250, and can be tuned by a fac-tor > C L by adjusting C R . These data demonstratethat Q can be tuned almost independently of the resonance fre-quency with a frequency variation of less than 0 .

22 % acrossthe entire C R range (see Figure 3b).For the minimum value of C L with the highest resonancefrequency, we calibrate the capacitance sensitivity of the cir-cuit for each Q by switching on and off the DUT MOM capac-itors C m =2, 3, and 8 fF and using double homodyne detection(II a) (see Figure 3c). The capacitance sensitivity α is ex-tracted from a least-square linear ﬁt of the phase change ∆φ = QC m / C p ≡ α C m for a given Q as shown in Figure 3d. Thesensitivity α increases linearly with Q from 0.76 to 1 . / fF.From the linear ﬁt in Figure 3d, we obtain C p =

137 fF, ingood agreement with the designed value (136 fF). In usualcircuits without an additional input capacitance , the para-sitic capacitance of the MOSFETs determines the resonancefrequency. In future design with accurate cryogenic compactmodels, this capacitance can be reduced signiﬁcantly leadingto higher resonance frequency and improved sensitivity.From C p and f r , we are now able to deduce the inductancevalue L . By adjusting C L , L varies from 2.42 to 5 .

18 µH.For a total footprint of 60 µm ×

50 µm, the active inductancedensity of 1 .

73 mH / mm is ﬁve orders of magnitude higherthan previously used passive inductors (55 nH / mm ) andthree orders of magnitude higher than superconding inductors Figure 3.

Characterization of the resonant circuit at 4.2 K for capacitance detection. a , Amplitude and phase of the demodulated circuitoutput V out for several active inductance settings. The resonance frequency shifts to lower frequency as the inductance value increases withincreasing C L (different colors). The continuous line (low- Q ) and dashed line (high- Q ) show the signals for different values of C R . b , Datapoints for the resonance frequency f r when the extracted Q is tuned with C R . The colored bars of width given by the written maximal deviationindicate the low dispersion of f r for ﬁxed C L when varying Q with C R . c , Measured phase shift for MOM capacitor C m of 2, 4, and 8 fF inseveral Q -factor settings. The capacitance sensitivity ∆φ / C m of the circuit is extracted from the slope with a least square ﬁt at given Q . d ,Capacitance sensitivity extracted from c as a function of the Q factor. A least square linear ﬁt of ∆φ / C m ( Q ) allows to extract the capacitance C p parallel with the active inductance. (1 . / mm ) . V. CAPACITANCE RESOLUTION

We now turn to the resolution in capacitance of the set-up,we derive the input-referred noise in aF / √ Hz from the signal-to-noise ratio (SNR) as a function of the integration time t int .For this, we generate a capacitance change by continuouslyconnecting and disconnecting C m = φ at f r with a rise time given by the integration timeis used to extract the signal power P sig and noise power P noise by separating the corresponding frequency components in thepower spectrum (see Supplementary Material IV). The result-ing SNR = P sig / P noise is used to extract the capacitance resolu-tion given by the equivalent C m ( SNR = ) = C m / SNR shownin Figure 4 as a function of t int from 100 ns to 100 µs. Acapacitance of 1 fF can be detected with an integration timeof 1 µs with SNR =

1. The capacitance resolution follows asquare-root law with t int from which we extract the equiva-lent input-referred noise of 3 . / √ Hz, two orders of mag-nitude higher than the best reported sensitivity using an ultra-low noise SQUID ampliﬁer .As correlated noise appears on time scales longer than 1 msoriginating probably from the 1 / f ﬂicker noise of the transis- tors, we add a second demodulation (IIa) at the capacitanceswitching frequency of 1 kHz to remove phase noise originat-ing from a varying L . The 1 kHz square-wave φ from (I) withan integration time of 100 µs is demodulated by (IIa) at 1 kHzto obtain its amplitude | φ | . The capacitance resolution as afunction of the second integration time for the 1 kHz demod-ulation is extracted by taking the ratio of the average and thestandard deviation of the | φ | signal and is shown in Figure 4.With an integration time of 1 s, the resolution becomes as lowas 10 aF. VI. QUANTUM CAPACITANCE MEASUREMENTS

With the calibrated impedancemetry circuit, we are able todetect the gate quantum capacitance C gg of the multiplexedtiny MOSFETs (M0, M1, M2 in Figure 2a) similar to theones used to implement spin qubits or single-electron tran-sistors for read-out with CMOS technology. Measurementswill be presented for M2 with a gate length of 120 nm and agate width of 80 nm. The other available device shows similarbehavior (see Supplementary Material V).The total gate capacitance C gg of such devices correspondsto the sum of the capacitance to drain, source, back-gate, andMOSFET channel of which the gate to channel capacitancedepends highly on the gate-source voltage V gs controlled by Figure 4.

Capacitance resolution of the measurement set-up.

Ex-trapolated capacitance C m at signal-to-noise ratio equal to 1 for sin-gle (I) (black circles) and double (IIa) (red squares) homodyne de-tection of the capacitance measurement as a function of the inte-gration time t int . Dashed lines are least-square ﬁts C m = a t − / int with a = √ . S c and S c the equivalent noise spectral density inaF / √ Hz of the capacitance measurement. the DC component of V bias (see Figure 2a). As C gg of nano-metric devices is extremely small compared to C p , we don’texpect to have sufﬁcient SNR for small capacitance variationsat reasonable integration times. Better sensitivity can be ob-tained by modulating V gs (method IIb) to measure after de-modulation the ﬁrst derivative dC gg / dV gs as C gg varies a lot ina small V gs window.While the resonator impedance is probed at 199 MHz, V gs is modulated at 1 kHz with mV-range excitation on V bias (seeFigure 2bc). The obtained result with a relatively large 25 mV V gs modulation (shown in Figure 5a) is reminiscent of thetypical gate capacitance variation around threshold voltage V th ≃ V bg = C gg (see inset of Figure 5a) reﬂects thetypical behavior for a FET capacitance from the subthresholdregime V gs ≪ V th to the strong inversion regime V gs ≫ V th .Upon decreasing the amplitude of the V gs modulation to only3 . dC gg / dV gs signal in Figure 5b revealsa ﬁne structure around V th consisting of successive peak-diposcillations. Following numerical integration, these featuresresult in a series of peaks in C gg , which we interpret as quan-tum contributions to the capacitance coming from electronstunneling in and out of localized quantum states within thetransistor channel.To further identify these quantum states, we acquire dC gg / dV gs for different back-gate voltage V bg from 2 to 6 Vas shown in Figure 5c. As V bg increases, all observed featuresshift to lower V gs with a slope close to the ratio β of gate-channel capacitance C g − ch over the backgate-channel capaci-tance C bg − ch alike the V th -shift with back-gate for similar FETdevices . For V bg > ×

80 nm de-vice (see Supplementary Material V). At lower V bg , the cou- pling increases with V gs from 10 to 14 as the electron-ﬁlledinversion layer is brought back to the top-interface.These measurements of integrated quantum devices demon-strate that the capacitive signature of structure in the elec-tronic density of states of quantum dots can be probed viaimpedancemetry. VII. CONCLUSIONS

We reported an integrated circuit that performsimpedancemetry of a resonator coupled to a quantumdot at cryogenic temperatures. The active inductance of theresonator allowed the controlled tuning of the resonancefrequency and quality factor, which will be of importancefor optimal frequency-spectrum crowding in multiplexedread-out schemes. The employed multiplexing of nanometricquantum devices with on-chip switches could be beneﬁcialfor reduced power per qubit in a scalable multi-qubit architec-ture. Novel read-out architectures with cryogenic electronics,such as the active inductance, have the potential to increasescalability and ﬂexibility in the design and exploitation ofquantum processors.Further work towards lower noise and lower power designwith more accurate high-frequency models at cryogenic tem-peratures will improve the ﬁnal performance. Measuring mul-tiplexed out-of-chip capacitances of quantum devices will bealso promising for the screening of quantum devices with asimpler experimental setup than reﬂectometry. In the long run,the realization of tailored high-end analog electronics at cryo-genic temperatures will improve and accelerate the up-scalingof quantum processors.

METHODS

Fabrication details.

The impedancemetry chip was de-signed in a commercial CMOS FD-SOI 28nm technologywith low- V th (LVT) thin-oxide (GO1) transistors. The chipis wire-bonded onto a QFN48 package directly soldered on a4-layer PCB with FR4 substrate. Measurement set-up.

The FR4 PCB is placed at the end ofa dip-stick enclosed in a metallic container ﬁlled with a smallamount of helium gas for thermal exchange with a liquid Hebath (see Supplementary Material VI). A PCB-mounted ther-mometer ensures a precise monitoring of the PCB tempera-ture. High-frequency lines of V in and V out are routed on thePCB from the chip package to the SMA coaxial connectorsvia top-layer 50 Ω -matched coplanar waveguide with groundplane and via fencing. Supply lines are decoupled fromenvironmental noise with PCB-mounted capacitors (0.1, 1,10 µF) and conveyed to room temperature with copper wiring.All other DC lines are conveyed to room-temperature with50 − Ω constantan wiring. At room temperature, elec-tronic apparatus comprises a multi-channel low-noise 21-bitdigital-to-analog converter, and a 600 MHz lock-in ampliﬁer. Figure 5.

Quantum capacitance measurement of an integrated MOSFET with channel length 120 nm and width 80 nm. a , Measurementof the ﬁrst derivative of the gate capacitance C gg with respect to V gs by applying a gate-source AC excitation of 25 mV. The inset shows thecapacitance C gg ( V gs ) computed from the integrated signal of the derivative. b , Expanded view of dC gg / dV gs around the off-on transition of theMOSFET measured with a smaller excitation of 3 . c , Evolution of dC gg / dV gs with the back-gate voltage V bg and the gate-source voltage V gs . The indicatedslopes β = dV bg / dV gs ≃ C g − ch / C bg − ch represent the relative coupling strength of the detected quantized states with respect to back- andfront-gate. DATA AVAILABILITY

The data that support the plots within this paper and otherﬁndings of this study are available from the corresponding au-thor upon reasonable request.

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ACKNOWLEDGEMENTS

This work was partly supported by the European Union’sHorizon 2020 research and innovation program under Grant Agreement No. 810504 (ERC Synergy project QuCube).

COMPETING INTERESTS

The authors declare a patent application FR1914651, ﬁledon december 17th 2019. r X i v : . [ qu a n t - ph ] F e b Supplementary Material: Compact gate-based read-out of multiplexedquantum devices with a cryogenic CMOS active inductor

L. Le Guevel,

1, 2, a) G. Billiot, S. De Franceschi, A. Morel, X. Jehl, A.G.M. Jansen, and G. Pillonnet Univ. Grenoble Alpes, CEA, LETI, F-38000 Grenoble, France Univ. Grenoble Alpes, CEA, Grenoble INP, IRIG, PHELIQS, F-38000 Grenoble, France (Dated: February 10, 2021)

I. READ-OUT SCALING OF LARGE QUBIT ARRAYS

Element Footprint Scaling(mm )Qubits 10 − m × N Ampliﬁers 0 . m Inductors 1 m × N Couplers 100 m Figure S1.

Reﬂectometry and scaling of large qubit arrays using directionnal couplers and passive inductors. a , Circuitry for simulta-neous read-out of large arrays of qubits using reﬂectometry with frequency multiplexing. To address N × N qubits in an array, N resonatorsat different resonant frequencies f r , i are each coupled to a row of N qubits frequency-multiplexed with f m , j . Resonators are probed with thescattering parameter S by sending a voltage excitation made of a frequency-comb f r , i . The incoming wave RF in and outgoing RF out wave areseparated with a directional coupler. The resonator frequency is deﬁned by the 50 Ω matching of the equivalent impedance of all resonatorsand differs from the LC resonant frequencies. RF out is sent to room-temperature demodulation with an ampliﬁer. Typical frequency-spectrumcrowding is represented in b-c . Frequency multiplexing for a given ﬁnite bandwidth and given read-out time imposes an upper-bound on thearray size N . As an example, for a read-out time of 1 µs and bandwidth of 1 GHz, N × N can only be as high as 100. To further increasethe number of qubits, each tile containing N × N qubits with the required circuitry is duplicated m times. The input frequency-comb voltageexcitation RF in is common to all tiles while the output signal RF out requires for each of them a coaxial line. d , Scaling laws in m and N and thetypical footprint for the circuit elements. The footprint of reﬂectometry is limited by the directional coupler size of ∼ (red square in a ). a) Electronic mail: [email protected]

Element Footprint Scaling(mm )Qubits 10 − m × N Source 10 − m × N Followers 10 − m × N Ampliﬁers 0 . m Inductors 1 m × N Figure S2.

Impedancemetry and scaling of large qubit arrays using passive inductors. a , Circuitry for simultaneous read-out of largearrays of qubits using impedancemetry with frequency multiplexing. To address N × N qubits in an array, N resonators at different resonantfrequencies f r , i are each coupled to a row of N qubits frequency-multiplexed at f m , j for current excitation via voltage-controlled currentsources. Each resonator ﬁlters the out-of-resonance components within the frequency comb f r , i of input excitation. The voltage responses ofeach resonator are added together and sent through an ampliﬁer to room-temperature demodulation for signal recovery of every single qubitresponse. Typical frequency-spectrum crowding is represented in b-c for the input and output signals. Frequency multiplexing for a given ﬁnitebandwidth and given read-out time imposes an upper-bound on the array size N . As an example, for a read-out time of 1 µs and bandwidth of1 GHz, N × N can only be as high as 100. To further increase the number of qubits, each tile containing N × N qubits is duplicated m times. Theinput frequency-comb voltage excitation RF in is common to all tiles while the output signal RF out requires for each of them a coaxial line. d ,Scaling laws in m and N and the typical footprint for the circuit elements. The footprint of impedancemetry is limited by the inductor size (redsquare in a ). Passive inductors with footprint of 1 mm can be replaced by controllable active inductors with a footprint of only 0 .

001 mm toimprove the circuitry scalability. II. DESIGN OF THE INTEGRATED CIRCUIT (cid:0)✁✂✄ ☎✁✂✄ ✆✝✂✄✞✟✠ ✞✡✡✞☛☛☞✌✍✎✏✑ ✒✓✔✕ ✖✗ ☞✘✍✙✒✚ ✖✗☞✛✜✛✢✣✤✥✦✧✛★✩☞✪✏✫✔✏✫✙✒✬✙✬✓ ✭✙✭✙✮ ✭✒✭✯ ✬✏ ✬✔ ✬✰✬✚✬✒✬✯ ✏✫✔✏✫✙✒ ✏✫✔✏✫✙✒✯✏✫✙✒✏✫✔✏✫✙✒✏✫✔✔✏✫✏✚ ✏✫✔✔✏✫✏✚ ✙✏✫✙✒ ✏✫✔✏✫✏✰ ✙✏✫✏✒✙✏✫✒ ✙✏✫✒✔✱✒✱ ✯✱ ✓✱ ✓✱ ✒✏✱✓✏✱ ✙✏✱☞✲✍✎✒✰✯✑ ✔✰✰✕ ✖✗ ✬✥✳✴✲✬✥✳✴✌ ✬✥✳✴✵ ✁✶✷✂✄✸✹✺☞✻✼✍✓✏✰ ✖✗✽✻✼✍✙✏ ✾✿ ❀✁✁✂✄✷✝✁✂✄ ❁❂❃❄❁❅❅ ❆ ❇ ❁ ❁❈❈

Figure S3.

Design implementation of the impedancemetry chip.

Details of the components with transistor dimensions in the integratedcircuit. The capacitor banks used as variable capacitors ( C L , C R , and C m ) are detailed in Figure S4 and S5. Each transistor dimension isindicated as m × WL with W (resp. L ) the gate-ﬁnger width (resp. length) of the gate in µm and m is the number of ﬁngers. The indicated currentreferences of the diode-mounted transistors are generated at room temperature (see Figure S16). (cid:0)✁✂✄☎ ✆✝ ✞✟✠✡☛ ✞✟✠✡☞(cid:0)✌✂✍✎ ✆✝ (cid:0)✏✂✑✄ ✆✝ (cid:0)✒✂✓✔✍ ✆✝ (cid:0)✁✂✎✔ ✆✝ (cid:0)✌✂✓☎✎ ✆✝☎✎✄ ✆✝✕✖✗✘✙✚✛ ✕✖✗✘✙✜✛ ✕✖✗✢✙✚✛✕✖✗✘✙✣✛ ✕✖✗✢✙✜✛✕✖✗✘✙✤✛✥ ✦✧★✩✧★✓☎ ✧★✩✧★✓☎ ✧★✩✧★✓☎ ✧★✩✧★✓☎ ✧★✩✧★✓☎ ✧★✩✧★✓☎ Figure S4.

Design implementation of the variable capacitors. a , Implementation of the variable capacitor C R at Node R in Figure S3. The4 binary-weighted MOM capacitors are selected with NMOS switches activated by the selection bits SEL R [ ] for C R variation from 0 to345 fF. b , Similar implementation of C L with 3 binary-weighted MOM capacitors in parallel from 362 to 566 fF. Figure S5.

Multiplexing of the Device Under Test (DUT). a , Design implementation of the capacitor bank with 3 MOM capacitors forcapacitive calibration and 3 nanometer-sized MOSFETs for quantum capacitance measurements. The MOM capacitors are selected withNMOS switches. The MOSFETs are selected with a pair of pass-gates as detailed in b . When the MOSFETs are unselected, the drainand source are set to ground while the selected-MOSFET drain and source are linked to V bias to change V gs . Pairs of pass-gate are madecomplementary (when one is OFF, the other one is ON) with one inverter as shown in c .ID Block name Area (mm ) Contribution (%)1 Current generation 0 . . . . .

865 Follower 0 . . . a b Figure S6.

Layout and footprint of the impedancemetry circuit. a , Layout view of the impedancemetry circuit. The labeled areas correspondto the circuit block names of table b . The bottom inset shows a zoomed window for the measured quantum devices. Each device is surroundedby dummies to improve the fabrication quality of the nanometer-sized devices. b , Table of the occupied area of each block for a total footprintof 0 .

004 mm . III. SIMULATION RESULTS AT 300 K

Figure S7.

Impedance of the active inductance from simulations at 300 K. a-d , Complex impedance of the active inductance for a few C R values with C L equal to: a b c d

566 fF. e-h , Quality factor Q of the active inductance as a function of C R extracted fromthe tank impedance. In a-d (respectively e-h ), stable resonance data with Q ≥ Q < i , Q as a function of the resonant frequency f r showingsmall dispersion. j , Evolution of f r with C L at all C R values. Figure S8.

Voltage-to-current conversion for the cur-rent excitation of the tank from simulations at 300 K.

Transimpedance G m and bandwidth of the current gener-ation as a function of frequency extracted from foundrymodels at 300 K.Figure S9. Ampliﬁer and follower characteristics from simulations at 300 K. a , Gain of the ampliﬁer as a function of frequency extractedfrom AC simulations with foundry models at 300 K. b , Gain of the follower loading a 50 pF cable capacitance at the chip output. c , Totalampliﬁcation of ampliﬁer and follower as a function of frequency. Despite large cable capacitance from 4.2 K to 300 K stage, the unity-gainbandwidth of 467 MHz allows to keep the gain above 1 at the resonant frequencies f r .Table I. Noise contribution from linear AC simulations at300 K.

Listed noise contributions of the 7 transistors generating84 % of the total output noise of the impedancemetry chip ex-tracted from foundry models at 300 K. The listed transistor de-vices belong to the active inductance which constitutes the mainsource of noise in the circuit. . Rank Device Contribution1 P1 25%2 N1 23%3 P1’ 14%4 P2 10%5 N4 5%6 N2 4%7 N3 3%

Figure S10.

Phase noise of the impedancemetry setup from300 K simulations.

Phase noise as a function of the frequency offsetwith respect to the resonance frequency of the tank f r =

167 MHzextracted at the chip output from Steady STate (SST) simulations at300 K with foundry models. The plateau above about 100 Hz withthe cut-off around ∼ κ ∼ f r / Q ≃ . Q =

81. From the plateau value of 2 m° / √ Hz, we estimatethe input-referred noise to 3 . / √ Hz. The appearance of a ﬂickercomponent in the phase noise is the evidence of the mixing between1 / f low-frequency noise and the tank high-frequency signal. Thisadditional non-linear noise is attributed to transistor noise that trans-lates into noise contribution to the inductance L and quality factor Q resulting in low-frequency noise up-mixing. IV. COMPLEMENTARY DATA OF THE RESONANT CIRCUIT AT 4.2 K

Figure S11.

Ampliﬁer and follower optimization at 4.2 K. a , Output voltage V out at the tank resonant frequency f r =

199 MHz as a functionof the ampliﬁer power at 4.2 K. To maximize the gain, we choose the operating power of the ampliﬁer at 150 µW. b , Output voltage V out at thetank resonant frequency f r =

199 MHz as a function of the follower power at 4.2 K. To maximize the gain, we choose the operating power ofthe follower at 2 . Extraction of the signal-to-noise ratio. a , Signal of the phase output after single demodulation (I) at the tank frequency f r when the DUT capacitance C m = b , Fourier power spectrum of φ with thetypical signature of a square wave with exponential transients with the harmonics 2 n +

1. The signal power spectrum related to the squarewave is isolated in d and the time-domain signal trace is recovered in c by inverted Fourier transform. The signal power P sig is computedby integrating the power spectrum of the signal. f , Noise power spectrum in φ extracted as the complementary power spectrum to the signalspectrum shown in b . The noise power P noise is computed by integrating the power spectrum of the noise. e , Time-domain noise extractedfrom f . The signal-to-noise ratio is extracted as the ratio of P sig / P noise and is equal to 5 . t c of 55 µs in this example. Figure S13.

Correlated noise in the resonator output signal at 4.2 K. a , Magnitude and phase of the output signal after demodulation atthe resonance frequency (method I). Clear correlations between magnitude and phase are observed as a function of time. Both the Spearman ρ S and Pearson ρ P computed on the entire time-trace exhibit strong anti-correlation between phase and magnitude with values of about − . b , 2D histogram in the I-Q plane of the data in a . The non-gaussian banana-shapedspot distribution reﬂects the evidence for correlated noise in the I-Q plane. This noise is attributed to transistor noise that leads to a noisyinductance value L and quality factor Q . V. MEASUREMENT OF THE GATE CAPACITANCE OF A DIFFERENT DUT

Figure S14.

Measurement of the N-type DUT transistor with L =

60 nm and W =

80 nm . a , First derivative of the gate capacitance dC gg / dV gs of a N-type MOSFET gate-capacitance as a function of the gate-source voltage V gs measured with the impedancemetry setup at4.2 K. Oscillations in the derivative capacitance is a sign of quantum capacitance from conﬁned electronic state in the MOSFET channel. b , dC gg / dV gs evolution with front-gate V gs and back-gate V bg voltages. All features shift to lower V gs for increasing V bg . No traces attributed toan impurity state with an anomalous slope as seen in Figure 5 in the main text are detected for this device. These measurements are the sameas presented in the main paper (Figure 5) for a longer device with L =

120 nm and W =

80 nm. VI. EXPERIMENTAL SETUP

Figure S15.

Experimental setup of the cryogenic sampleholder.

Picture of the PCB ( a ) with soldered QFN48 ( b ), andwire-bonded integrated circuit ( c ). The PCB mounted at the endof a dip-stick is enclosed in a metallic tube ﬁlled with He gas forthermal exchange with a liquid helium bath at 4.2 K. High fre-quency signals are routed to SMA connectors at the end of thePCB with grounded coplanar waveguides and conveyed to roomtemperature with coaxial cables. SMD capacitors close to thechip reject the noise at sensitive voltage nodes ( V DD , V SS ,. . . ). (cid:0)✁✁ (cid:0)✁✁✂✄☎✆ ✂☎✆ ✄✝✂☎✆ ✞✟✠✡☛☞✌✠✡✍ ✎✏✑✒✎✓✒✒✡☞ ✔✕✖✗✘✙✑☞✑✟☛ ✚✌✠✡☞✑✌✛✜✎✓✟✢✠✌✟✠✌✟ ✔✣✤✥✖✦✤✗✘ ✧✓★✩✥✑✟ ✪✫✒✛✑✬✡☞✭✞ ✮✯✰✧✞✞✠✡✢✠ ✱✞✧✲✳✴ ✱✵✶✷✶✷✴ ✎☞✸✓★✓✟✰✥(cid:0) ✰✥(cid:0) ✰✥(cid:0)✹ ✺✻✼✥(cid:0) ✼✥(cid:0) ✼✥(cid:0) ✽✾✿❀❁❂❃❄✎✓✌✴✑✌✛✛✑✟✡✢ ✣✤❅ ✞✟✒❆✠(cid:0)❇❈❉(cid:0)❊❋(cid:0)●● (cid:0)●● (cid:0)❍■ (cid:0)❏❑▲▼❁▼❃◆❖❂P ❀❖◆◗ ❘❙❚❯ ❘❙❱❲❳❨❩❬ ❭❪✎✱✥✫✓❆✟✠✡✍✲✏✡☞✫✓✫✡✠✡☞❪✎✱✥✫✓❆✟✠✡✍❫✡★✓❆✒✛✑✟☛✎✌✒✌★✑✠✓☞✢ ❴❵❵ ❭✞❛(cid:0)❛ ✞✥ (cid:0)✥ Figure S16.

Instrumentation with connections to the chip.