Contact-Barrier Free, High Mobility, Dual-Gated Junctionless Transistor Using Tellurium Nanowire
Pushkar Dasika, Debadarshini Samantaray, Krishna Murali, Nithin Abraham, Kenji Watanabe, Takashi Taniguchi, N. Ravishankar, Kausik Majumdar
CContact-Barrier Free, High Mobility, Dual-Gated Junctionless Tran-sistor Using Tellurium Nanowire
Pushkar Dasika Debadarshini Samantaray Krishna Murali Nithin Abraham Kenji Watanabe TakashiTaniguchi N. Ravishankar Kausik Majumdar
Pushkar Dasika, Krishna Murali, Nithin AbrahamDepartment of Electrical Communication Engineering,Indian Institute of Science, Bangalore 560012, IndiaEmail Address:[email protected] Samantaray, N. RavishankarMaterials Research Center,Indian Institute of Science, Bangalore 560012, IndiaKenji WatanabeResearch Center for Functional Materials, National Institute for Materials Science,1-1 Namiki, Tsukuba 305-044, JapanTakashi TaniguchiInternational Center for Materials Nanoarchitectonics, National Institute for Materials Science,1-1 Namiki, Tsukuba, 305-044 JapanKeywords:
Tellurium, nanowire, high mobility, barrier-free, dual-gate
Gate-all-around nanowire transistor, due to its extremely tight electrostatic control and vertical integration capability, is a highlypromising candidate for sub-5 nm technology node. In particular, the junctionless nanowire transistors are highly scalable with re-duced variability due to avoidance of steep source/drain junction formation by ion implantation. Here we demonstrate a dual-gatedjunctionless nanowire p -type field effect transistor using tellurium nanowire as the channel. The dangling-bond-free surface due tothe unique helical crystal structure of the nanowire, coupled with an integration of dangling-bond-free, high quality hBN gate dielec-tric, allows us to achieve a phonon-limited field effect hole mobility of 570 cm / V · s at 270 K, which is well above state-of-the-artstrained Si hole mobility. By lowering the temperature, the mobility increases to 1390 cm / V · s and becomes primarily limited byCoulomb scattering. The combination of an electron affinity of ∼ µ A /µ m whilemaintaining an on-off ratio in excess of 2 × . The findings have intriguing prospects for alternate channel material based next-generation electronics. The tight electrostatic control in multi-gated nanowire field effect transistor (FET) [1, 2, 3, 4] makes itone of the most promising candidates for further scaling of silicon technology in sub-5 nm technologynodes, and is being actively pursued by the semiconductor industry [5, 6]. The possible vertical inte-gration of multiple nanowires enhances the drive current at a given footprint [7, 6]. In parallel, severalhigh-mobility, non-silicon channel options are being actively pursued as well, particularly for the p-FET[8, 9, 10].Three technological roadblocks must be overcome to achieve these high performance, ultra-scaled de-vices. First, the source-drain electrical isolation in a transistor is usually achieved by doping. The re-quired spatial steepness of the doping profile is non-trivial to achieve in such ultra-short channel nanowireFETs. It also adds to the large variability, resulting in low yield. In this direction, junctionless FET hasattracted a lot of attention for high scalability [11, 12] where one uses a narrow conducting channel, andthe gate voltage is used to deplete the carriers from the channel to turn it off, thus avoiding source-drainjunction formation through ion implantation. Second, since the nanowire must be very narrow to achievethe required gate control, the surface roughness scattering is enhanced [13, 14], significantly degradingthe carrier mobility. A nanowire channel with dangling-bond-free surface will be ideally suited to reducesuch mobility degradation. Third, as the device footprint goes down with transistor scaling, the effectivecontact area at the source and drain reduces. This increases the fraction of the contact resistance in thetotal transistor resistance under on condition, which is detrimental to the overall drive current, switching a r X i v : . [ c ond - m a t . m e s - h a ll ] F e b peed, current saturation, and output resistance [15]. One must use novel techniques to reduce contactresistivity.In an attempt to address the above-mentioned issues, here we use a dual-gated tellurium (Te) nanowirejunctionless transistor. The unique chiral nature of the nanowire crystal structure [16, 17] allows a highhole mobility due to dangling-bond-free surface, and its low electron affinity helps us to achieve zero Schot-tky barrier at the contact interface, reducing the contact resistance. We achieve a drive current of 216 µ A /µ mwith an on-off ratio of > × and a high hole mobility of 570 cm / V · s.Te is an element in the chalcogen group, and its crystal structure consists of covalently bonded one-dimensionalchains of Te along the c-axis that are held together by weak van der Waals interactions [inset of Fig.1(a)]. Thus, the nanowire form of Te is predominantly bound by lower energy surfaces that are producedby only breaking the weak van der Waals bonds and not the strong covalent bonds, leading to dangling-bond-free surface of the nanowire. This unique anisotropic crystal structure of Te provides an opportu-nity to synthesize nanowires of Te down to single chain Te atoms [18, 17].Tellurium, in its bulk form, has a bandgap of 0.35 eV and exhibits p -type nature [19] with high carriermobility [20]. As the bulk Te is reduced to smaller dimensions, it starts exhibiting an indirect bandgapof about 0.6 eV [21, 17]. In addition to these electrical properties, Te also shows remarkable optical, ther-moelectric, and piezoelectric properties [22, 23, 24, 25]. Te nanowires are synthesized (see
Methods for details) using Na TeO as a precursor in the water medium,where hydrazine hydrate is used as a reducing agent, PVP as a capping agent, and Ammonia is used tomaintain proper pH. After the reaction and cool down to room temperature, the solution is sonicatedtwelve times using hot water (60 ◦ C) at 8000 revolutions per minute and subsequently two times usingethanol.
Structural and microstructural characterization of Te nanowire:
As synthesized Te nanowires have beencharacterized by X-ray diffraction (XRD) using Rigaku X-ray Diffractometer with Cu K α source. Fig.1(a) represents the XRD pattern of the nanowire which corresponds to the rhombohedral phase (P3 .
45 ˚A, c = 5 . . − corresponding to the A mode oflattice vibration at the Brillouin zone center [26, 27]. The E T O zone center modes of vibration manifestas another strong Raman peak at 142 . − and a weak shoulder around 103 cm − [26, 28]. We assignthe broad peak around 265 cm − to second order Raman peak corresponding to A + E T O two-phononprocess [29].
Device Fabrication:
The step-by-step fabrication process of the junctionless FET is illustrated in Fig.2(a). We drop cast the Te nanowires onto a degenerately doped Si substrate coated with 285 nm thick,thermally grown, high quality SiO . A low power Ar treatment is then performed to remove any resid-ual PVP coating from the nanowires. A thin layer of high-quality hBN ( ∼
15 nm) is immediately trans-ferred onto the nanowire using a dry transfer technique [30] to define the top gate dielectric. The atomi-cally smooth surface of dangling-bond-free hBN gate dielectric provides an ideal interface with the dangling-bond-free Te nanowire channel. Subsequently, electron beam lithography is performed to define the source, he drain, and the gate metallization areas. To remove any unintentional residue and surface oxidation[31] from the source/drain region of the nanowire, a second plasma cleaning step is performed, which im-proves the contact interface quality. Ni/Au is then deposited using DC magnetron sputtering, followedby lift-off in acetone to complete the device fabrication. More details of the fabrication are provided in Methods .We find that an optimum plasma cleaning is a crucial step in the fabrication, which helps remove resid-ual PVP capping layer and possible interfacial oxide, improving the interface quality and reducing thecontact resistance. A careful optimization shows that Ar plasma cleaning for 20 s at a power level of 10W and a pressure of 10 mbar results in the optimum device performance. The Figs. 2(b)-(c) show theSTEM images of two different nanowires, one without the plasma cleaning and the other after plasmacleaning for 20 s, respectively. The plasma cleaned nanowire clearly shows superior surface quality. Theelectrical characteristics of a nanowire without plasma cleaning are shown in Fig. 2(d) at various tem-peratures from 7 to 200 K. The characteristics show very low current levels and fast current saturation.Such an observation has also been made previously for devices using two-dimensional layer materials[32]. On the other hand, the nanowires with plasma cleaning show a 1000-fold enhancement in the cur-rent drive at similar external bias, indicating superior contact quality as shown in 2(e)
We measured several devices with a typical diameter of the nanowires chosen between 30 to 50 nm. Thenanowires, with a low bandgap [33], exhibit strong p-type conductivity, even without any gating. Thisallows us to operate the fabricated transistor as a dual -gated junctionless nanowire FET, as schemat-ically illustrated in Fig. 3(a). The plan view SEM image of a typical nanowire FET is shown in Fig.3(b). The cross-section of the device along the white dashed line is provided in
Supporting Figure 1 .The transistor is normally in the on state and requires a positive gate voltage to deplete the holes fromthe channel (depletion mode). The top gate using the hBN dielectric controls the channel conductivity,while the global back gate can control both the channel portion, as well as the underlap regions and themetal contact region. This allows us to avoid the need for source/drain doping, and the device works asa junctionless transistor.The modulation of the drain current ( I D ) as a function of both the top ( V T G ) and the bottom ( V BG )gate voltages is shown as a two-dimensional color plot in Fig. 3(c), at V D = − . V T G [along (i)] or V BG [along (ii)]. Since the transistor is operated in depletion mode, theapplication of a negative V T G and V BG does not improve the drive current significantly, as can be seenfrom the characteristics. However, a positive gate voltage efficiently modulates I D by depleting the holesfrom the channel. While the obtained on-off ratio is ∼ using either the top or the bottom gate sepa-rately, we achieve an on-off ratio over 2 × when the two gates are simultaneously used. The results ofa coupled electrostatics and carrier transport simulation from a junctionless transistor are summarized in Supporting Figure 2 .The output characteristics of the device are shown in Fig. 3(e-f), which are obtained by sweeping V T G while keeping V BG at 30 and −
30 V, respectively. Since the global back gate can modulate the effectivebarrier to hole injection, at V BG = 30 V, the barrier to hole injection is high, and hence the output char-acteristics show a predominantly Schottky behaviour. However, at V BG = −
30 V, the barrier to hole in-jection is removed, and the underlap regions are electrostatically p-doped, leading to output character-istics tending towards current saturation behavior. Thus, by changing the biasing configuration, we areable to convert the device operation from a Schottky barrier FET (SBFET) to a MOSFET. Similar ar-chitecture has previously been employed with Silicon nanowire transistors [35, 36] wherein a combinationof a top gate and a back gate has been utilized to improve the on-off ratio. In the MOSFET mode, we chieve a high drive current of 216 µ A /µ m (calculated using I D πr where r is the radius of the nanowire)from the nanowire FET. Given the relaxed geometry used in this work, this is very promising towardshigh performance scaled transistor.A qualitative band diagram of metal (Ni) - Te junction is shown in Fig. 4(a) at equilibrium. The elec-tron affinity of Te χ T e ≈ φ m ≈ φ m (cid:29) φ s where φ s isTe work function. This allows the holes to move freely across the contact interface without any Schottkybarrier and is ideal for an excellent ohmic contact [37].To analyze such contact barrier-free operation in the MOSFET mode, we measure the temperature-dependentdevice characteristics keeping the bottom gate floating, and varying V T G and V D . The transfer character-istics of the device from 5 to 270 K are shown in Fig. 4(b). It is striking that under on condition ( V T G < I D is a very weak function of temperature, even down to temperatures as low as 5 K, and I D increaseswith a reduction in temperature (due to a subsequent increase in hole mobility, as discussed later) - clearlysuggesting barrier-free hole injection from the contact.We further verify this using modified Richardson equation for nanowire [38] in Fig. 4(c), wherein theinset, we plot I D T in the log scale as a function of T at various V T G . The effective barrier height, as ex-tracted from the slope of the linear fits, is shown in Fig. 4(c). The positive slope (and hence the ‘nega-tive’ effective barrier) under on state is due to a reduction in I D with T , representing a negligible barrierat the contact interface. This is independent of V T G as the top gate only controls the channel portion.At larger positive V T G , the extracted effective barrier increases, which corresponds to the V T G inducedpotential barrier created between the source underlap and the channel, as the channel turns off. Theoutput characteristics of the device shown in Fig. 4(d) further supports the negligible Schottky barriereven at T = 5 K . The characteristics show strong current saturation, particularly at relatively low | V T G | ,and I D varies approximately in a quadratic manner with V T G .Using the temperature dependent transfer characteristics, we extract the field effect mobility ( µ ) of thenanowire FET as [10, 39] µ = dI D dV T G L ch C ox V (cid:48) D (1)Here C ox is the gate capacitance per unit length of the device, L ch is the channel length of the device,and V (cid:48) D is the effective drain bias after correcting for the series resistance. Since the gate does not en-tirely cover the device, there are significant underlap regions which contribute to the series resistance.This effect can be seen in output characteristics shown in Fig. 4(d) where at high | V T G | , the rate of in-crease of current with V T G decreases, indicating that I D is limited by the series resistance. The total se-ries resistance is estimated as R s = R D L under L wire (2)where R D is the output resistance in the linear regime with V T G ≈ L wire is the total length of thenanowire and L under (= L wire − L ch ) is the total length of the underlap regions. The corrected drain biasthen becomes V (cid:48) D = V D − I D R s (3)where V DS is the applied drain bias.The channel being cylindrical in nature, C ox is very sensitive to device geometry and can vary up to 10-fold if the correct device structure is not taken into account [40, 41, 42]. The cross sectional geometry ofthe device and the corresponding scanning electron micrograph are shown in Fig. 5(a-b). To accuratelycapture the gate capacitance, Laplace equation is solved for this device geometry ∂ φ∂x + ∂ φ∂y = 0 (4)using finite element method (FEM) as implemented in FreeFEM++ software [43]. The nanowire is as-sumed to be conducting and hence is equipotential with Dirichlet boundary conditions φ = V . The topsurface of hBN is assumed to have fixed potential at φ = 0. Since the bottom gate in the measurement is eft floating, the electric field at the bottom of 285 nm SiO is assumed to be zero. The total charge ( Q )on the nanowire is calculated by integrating the normal component of the electric field on the nanowire.The gate capacitance is then obtained from C = QV . The electrostatic potential contour lines and thecorresponding electric field lines as obtained from the 2D FEM simulation is shown in Fig. 5(d). Dueto the relatively larger diameter of the nanowires used in this work, we have neglected the quantum ca-pacitance of the channel [44, 45, 46] arising from the finite density of states. This quantum capacitancecomes in series with the gate oxide capacitance calculated above. This results in a slight overestimationof the gate capacitance, hence underestimating the extracted carrier mobility. Thus the extracted holemobility values discussed next represent the lower bounds of the true mobility.The extracted µ is shown in Fig. 5(c) as a function of V T G at different T . µ has a peak ( µ peak ) near thethreshold voltage, where it shows strong temperature dependence. On the other hand, at higher neg-ative V T G , it drops due to large gate field [47], and the strong temperature dependence vanishes. Thenanowire FET exhibits µ peak = 570 cm / V · s at 270 K, which is twice of (110) Si hole mobility, andalso beats the state-of-the-art uniaxially compressed (110) strained Si hole mobility [4]. µ peak increasesmonotonously with a decrease in the temperature initially, and gradually saturates to a value of 1390 cm / V · sat low temperature [Fig. 5(e)]. For T >
180 K, µ peak can be fitted to a power law: µ peak ∝ T − γ (5)with γ = 1 .
47. This indicates that for T >
180 K, µ peak is limited by phonon scattering, while at lowertemperatures, it is limited by Coulomb scattering [48, 49]. For solution synthesized Te nanoflakes, γ hasbeen found to be 1.03 [50] while in Te thin films grown by molecular beam epitaxy, γ is found to varybetween 0.75 to nearly zero [51].A comparison of performance of the presented Te nanowire transistor with other reported Te-based tran-sistors [34, 16, 51, 50, 52, 17] is shown in Fig. 5(f-g) in terms of drive current and on-off ratio. To makea fair comparison by accommodating varied device dimensions and biasing conditions in reported datafrom the literature, we scale the drive current ( I ON ) by the drain field and the circumference of the nanowire(channel width in case of 2D flakes) as follows: I scaled = I ON L wire πrV DS (6)Previous reports suggest that Te exhibits high mobility for thicker films (and wider nanowires); however,it becomes challenging to turn the channel off at such channel thickness. On the other hand, for thinchannels, where the on-off ratio is improved, the carrier mobility degrades significantly, and Te loses itsattractiveness as a high-mobility channel. Fig. 5(f) shows the on-off ratio achieved in various Te-basedtransistor structures reported earlier as a function of the channel thickness (or diameter), suggesting astrong degradation of the on-off ratio for thicker channels. From the same figure, we observe that theadvantage of the improved electrostatics due to dual-gated nanowire structure in the present work is re-markable, allowing us to achieve an on-off ratio of 2 × (@ V ds = − . / V · s at 270 and 5 K, respectively), dangling-bond-free, clean interface between the nanowire channel and hBN dielectric, and dual-gated operation allowsus to achieve an on-off ratio in excess of 2 × with a high on-current of 216 µA/µm even at a relativelysmall drain field, which is superior to existing p-type nanowire FETs. Te nanowires are thus a promisingcandidate for next-generation ultra-scaled transistors, as well as for other nanowire-based electronic ap-plications, including highly scaled memory, biosensing, fast infrared sensing, and spectroscopy. ethods Chemical synthesis of Te nanowires
The Te nanowires are synthesized [21] using Na TeO as a precursor in the water medium, where hy-drazine hydrate is used as a reducing agent, Polyvinylpyrrolidone( PVP) as a capping agent, and Am-monia is used to maintain proper pH. In a typical experiment, 1 g of PVP (average. M.W.= 58,000) isdissolved in 20 ml of DI water and 92 mg Na TeO is dissolved in 15 ml DI water separately. Both solu-tions are mixed at room temperature. Into the above solution, 1.5 ml of Hydrazine hydrate and 3.3 mlof 25% aqueous ammonia solution are added drop-wise with a moderate stirring. The transparent solu-tion is then transferred to a 50 ml capacity teflon container. Then the hydrothermal reaction is allowedto take place for 4 hours at 180 ◦ C. After the reaction vessel cools down to room temperature, the solu-tion is cleaned twelve times using hot water (60 ◦ C) at 8000 revolutions per minute and subsequently twotimes using ethanol.
Material and structural characterization
X-ray diffraction measurement has been carried out using Rigaku X-ray Diffractometer with Cu K α source.Microstructural characterization has been done using FEI Tecnai T20 S-Twin (200 kV) and FEI-TitanG2 60-300 microscope operated at 300 kV. To get a cross-sectional view of the device, the desired pat-tern has been made using FEI Helios G4 UX FIB instrument with Ga ion beam source operated at 30kV (current ∼ . ∼ Device fabrication and characterization
The solution synthesized nanowires were first drop cast on p ++ Si substrate with 285 nm SiO grown ontop. The substrate is the Argon plasma cleaned at a power of 10 W and a pressure of 10 mbar for 20 sin PlasmaLab system 100 ICP 380 from Oxford instruments. A thin layer of hBN is then transferred us-ing a dry transfer method. The substrate is then spin-coated with PMMA C3 and baked on a hot plateat 180 ◦ C for 2 minutes. e-Beam lithography is then performed to define the source, drain, and gate con-tacts. Patterns are then developed in MIBK:IPA solution in 1:3 ratio. Substrate is then immediatelyplasma cleaned once again using the same parameters. Ni/Au (20 nm/40 nm) is then deposited on thesubstrate using DC magnetron sputtering. Finally, lift-off is performed by dipping the substrate in ace-tone for 10 minutes, followed by drying.Room temperature device characterization was done in ambient conditions using a B1500 semiconductorparameter analyzer. Low-temperature characterization was performed by loading the substrate in Mon-tana cryostation using a Keithley 4200A semiconductor parameter analyzer.
Acknowledgements
The authors acknowledge the electron microscopy facilities at the Advanced Facility for Microscopy andMicroanalysis, IISc. K. M. acknowledges the support a grant from Indian Space Research Organization(ISRO), a grant from MHRD under STARS, grants under Ramanujan Fellowship and Nano Mission fromthe Department of Science and Technology (DST), Government of India, and support from MHRD, Me-itY and DST Nano Mission through NNetRA. K.W. and T.T. acknowledge support from the Elemen-tal Strategy Initiative conducted by the MEXT, Japan, Grant Number JPMXP0112101001, JSPS KAK-ENHI Grant Numbers JP20H00354 and the CREST(JPMJCR15F3), JST.
References [1] Y. Cui, Z. Zhong, D. Wang, W. U. Wang, C. M. Lieber,
Nano letters , , 2 149.[2] N. Singh, A. Agarwal, L. Bera, T. Liow, R. Yang, S. Rustagi, C. Tung, R. Kumar, G. Lo, N. Bala-subramanian, et al., IEEE Electron Device Letters , , 5 383.
3] J. Appenzeller, J. Knoch, M. T. Bjork, H. Riel, H. Schmid, W. Riess,
IEEE Transactions on elec-tron devices , , 11 2827.[4] K. J. Kuhn, IEEE transactions on Electron Devices , , 7 1813.[5] M. T. Bohr, I. A. Young, IEEE Micro , , 6 20.[6] L. Armasu .[7] B.-H. Lee, J. Hur, M.-H. Kang, T. Bang, D.-C. Ahn, D. Lee, K.-H. Kim, Y.-K. Choi, Nano letters , , 3 1840.[8] K. Ikeda, M. Ono, D. Kosemura, K. Usuda, M. Oda, Y. Kamimuta, T. Irisawa, Y. Moriyama,A. Ogura, T. Tezuka, In . IEEE, IEEE electron device letters , , 3 211.[10] D. Wang, Q. Wang, A. Javey, R. Tu, H. Dai, H. Kim, P. C. McIntyre, T. Krishnamohan, K. C.Saraswat, Applied Physics Letters , , 12 2432.[11] C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, J.-P. Colinge, Applied Physics Letters , , 5 053511.[12] S. Gundapaneni, S. Ganguly, A. Kottantharayil, IEEE Electron Device Letters , , 10 1325.[13] S. Jin, M. V. Fischetti, T.-w. Tang, Journal of Applied Physics , , 8 083715.[14] E. Ramayya, D. Vasileska, S. Goodnick, I. Knezevic, Journal of Applied Physics , , 6063711.[15] K. Majumdar, N. Bhat, P. Majhi, R. Jammy, IEEE transactions on electron devices , , 92264.[16] F. Liang, H. Qian, Materials Chemistry and Physics , , 2-3 523.[17] J.-K. Qin, P.-Y. Liao, M. Si, S. Gao, G. Qiu, J. Jian, Q. Wang, S.-Q. Zhang, S. Huang, A. Charnas,et al., Nature Electronics , , 3 141.[18] P. V. Medeiros, S. Marks, J. M. Wynn, A. Vasylenko, Q. M. Ramasse, D. Quigley, J. Sloan, A. J.Morris, ACS nano , , 6 6178.[19] C. Zhao, C. Tan, D.-H. Lien, X. Song, M. Amani, M. Hettick, H. Y. Y. Nyein, Z. Yuan, L. Li, M. C.Scott, et al., Nature Nanotechnology , , 1 53.[20] Z. Zhu, X. Cai, S. Yi, J. Chen, Y. Dai, C. Niu, Z. Guo, M. Xie, F. Liu, J.-H. Cho, et al., Physicalreview letters , , 10 106101.[21] A. Roy, K. R. Amin, S. Tripathi, S. Biswas, A. K. Singh, A. Bid, N. Ravishankar, ACS applied ma-terials & interfaces , , 23 19462.[22] T. I. Lee, S. Lee, E. Lee, S. Sohn, Y. Lee, S. Lee, G. Moon, D. Kim, Y. S. Kim, J. M. Myoung,et al., Advanced Materials , , 21 2920.[23] A. Pradhan, A. Roy, S. Tripathi, A. Som, D. Sarkar, J. K. Mishra, K. Roy, T. Pradeep, N. Ravis-hankar, A. Ghosh, Nanoscale , , 27 9284.[24] G. Qiu, S. Huang, M. Segovia, P. K. Venuthurumilli, Y. Wang, W. Wu, X. Xu, P. D. Ye, Nano let-ters , , 3 1955.[25] S. Lin, W. Li, Z. Chen, J. Shen, B. Ge, Y. Pei, Nature communications , , 1 1.
26] A. Pine, G. Dresselhaus,
Physical Review B , , 2 356.[27] Y. Du, G. Qiu, Y. Wang, M. Si, X. Xu, W. Wu, P. D. Ye, Nano Letters , , 6 3965.[28] J.-W. Liu, F. Chen, M. Zhang, H. Qi, C.-L. Zhang, S.-H. Yu, Langmuir , , 13 11372.[29] J.-M. Song, Y.-Z. Lin, Y.-J. Zhan, Y.-C. Tian, G. Liu, S.-H. Yu, Crystal Growth and Design , , 6 1902.[30] A. Castellanos-Gomez, M. Buscema, R. Molenaar, V. Singh, L. Janssen, H. S. J. van der Zant,G. A. Steele,
2D Materials , , 1 011002.[31] W.-J. Lan, S.-H. Yu, H.-S. Qian, Y. Wan, Langmuir , , 6 3409.[32] P.-H. Ho, Y.-R. Chang, Y.-C. Chu, M.-K. Li, C.-A. Tsai, W.-H. Wang, C.-H. Ho, C.-W. Chen, P.-W. Chiu, ACS Nano , , 7 7362.[33] G. Haeffler, A. E. Klinkm¨uller, J. Rangell, U. Berzinsh, D. Hanstorp, Zeitschrift f¨ur Physik DAtoms, Molecules and Clusters , , 3 211.[34] Y. Wang, G. Qiu, R. Wang, S. Huang, Q. Wang, Y. Liu, Y. Du, W. A. Goddard, M. J. Kim, X. Xu,et al., Nature Electronics , , 4 228.[35] S.-M. Koo, Q. Li, M. D. Edelstein, C. A. Richter, E. M. Vogel, Nano letters , , 12 2519.[36] A. Colli, A. Tahraoui, A. Fasoli, J. M. Kivioja, W. I. Milne, A. C. Ferrari, ACS nano , , 61587.[37] R. F. Pierret, Semiconductor device fundamentals , Pearson Education India, .[38] M. F. O’Dwyer, R. A. Lewis, C. Zhang,
Microelectronics journal , , 3-4 597.[39] S. M. Sze, K. K. Ng, Physics of semiconductor devices , John wiley & sons, .[40] D. Khanal, J. Wu,
Nano letters , , 9 2778.[41] O. Wunnicke, Applied Physics Letters , , 8 083102.[42] M. S. Fuhrer, J. Hone, Nature nanotechnology , , 3 146.[43] F. Hecht, J. Numer. Math. , , 3-4 251.[44] M. Fickenscher, T. Shi, H. E. Jackson, L. M. Smith, J. M. Yarrison-Rice, C. Zheng, P. Miller,J. Etheridge, B. M. Wong, Q. Gao, et al., Nano letters , , 3 1016.[45] K. Pemasiri, H. E. Jackson, L. M. Smith, B. Wong, S. Paiman, Q. Gao, H. Tan, C. Jagadish, Jour-nal of Applied Physics , , 19 194306.[46] Y. Lee, K. Kakushima, K. Natori, H. Iwai, IEEE transactions on electron devices , , 4 1037.[47] S.-i. Takagi, A. Toriumi, M. Iwase, H. Tango, IEEE Transactions on Electron Devices , , 122357.[48] Z.-Y. Ong, M. V. Fischetti, Physical Review B , , 16 165316.[49] B. Radisavljevic, A. Kis, Nature materials , , 9 815.[50] M. Amani, C. Tan, G. Zhang, C. Zhao, J. Bullock, X. Song, H. Kim, V. R. Shrestha, Y. Gao, K. B.Crozier, et al., ACS nano , , 7 7253.[51] G. Zhou, R. Addou, Q. Wang, S. Honari, C. R. Cormier, L. Cheng, R. Yue, C. M. Smyth, A. La-turia, J. Kim, et al., Advanced Materials , , 36 1803109.
52] L. Tong, X. Huang, P. Wang, L. Ye, M. Peng, L. An, Q. Sun, Y. Zhang, G. Yang, Z. Li, et al.,
Na-ture communications , , 1 1. upporting Figure 1: Cross section view of the nanowiretransistor Figure 1: (a) Plan-view scanning electron micrograph for a nanowire FET. (b) Focussedion beam cut along the dashed line in (a). (c-d) Schematic (in c) and scanning electronmicrograph (in d) of the cross section of the device when cut along the dashed line in (a).2 upporting Figure 2: Drift diffusion simulation of junc-tionless FET
To gain deeper understanding of operation of junctionless transistor, drift diffusion simulationhave been performed assuming a charge sheet model and solving Shockley equations selfconsistently. Band gap of the material is assumed 0.6 eV, default doping is defined by E F − E V = 0 . − − − D [V] I D [ a . u ] V G = 0 to -2 V − − G [V]0204060 I D [ μ A / μ m ] V D = − [ a . u ] μ m] − − − E n e r gy [ e V ] E C E V V G = 0 to -0.5 V DrainChannelSource (a) (b)(c)
Figure 2: (a) Output and (b) transfer characteristics of the device showing the saturationof current at more negative top gate voltage. Although the characteristics follow square lawnear threshold, but start saturating at more negative gate bias. (c) Band profile of the deviceat various gate biases, keeping a small drain bias.3 igure 1: (a) X-ray diffraction pattern of Te nanowires, which correspond to P
21 rhombohedral phase of Te. Inset:Crystal structure of hexagonal Te chains along the c axis. Solid lines indicate covalent bonding, while each chain is bondedto other by van der Waals bonds. (b) TEM image of the nanowires. (c) SAED from Te nanowire (bright-field image shownin the inset) showing single-crystalline nature (corresponding to [1¯10] zone axis). (d) HRTEM image of the Te nanowirewhere the lattice fringes correspond to (001) plane of Te. (e) High-resolution HAADF-STEM image of Te nanowires show-ing the atomic layers. (f) Raman spectroscopy of Te nanowire showing first order and second order peaks.12 e-beam litho-graphy &development Metal deposition & lift-off Ar plasma etching
50 nm 50 nm50 nm b c
50 nm 50 nm50 nm b c −2 −1 0 1 2Drain bias [V]−3−2−101 D r a i n c u rr e n t [ n A ] V TG = 0 T = 7 K50 K100 K150 K200 K −2 −1 0 1 2Drain bias [V]−2−1012 D r a i n c u rr e n t [ μ A ] V TG = 0 V (a)(d) (e) Figure 2: (a) Step-by-step process flow of Te nanowire junctionless FET fabrication. (b,c): HAADF-STEM image of Tenanowire (b) without plasma cleaning, and (c) with plasma cleaning for a duration of 20 sec. (d) Temperature dependentcurrent-voltage characteristics of a nanowire device without plasma cleaning with low current levels and abrupt currentsaturation. (e) Characteristics of the device at room temperature with plasma cleaning showing higher current levels andohmic behaviour. 13 e NWh-BNTGD BG S
Te NW h-BN (b)
D TGS μ A10 μ A (iii)(i)(ii) Top gate bias [V] B ac k g a t e b i a s [ V ] (i) (iii)(ii) Drain bias [V] D r a i n c u rr e n t [ μ A ] V TG = 0 to 2 V (steps of 0.5 V) Drain voltage [V] D r a i n c u rr e n t [ μ A ] V TG = 0 to 2 V(steps of 0.5 V) (a)(c) (d)(e) (f) Figure 3: (a) Schematic representation of the dual-gated nanowire junctionless FET. (b) Scanning electron micrograph ofthe device. Scale bar is 5 µ m. (c) Two-dimensional color plot of the drain current magnitude as the top gate V T G and backgate V BG voltages are varied at V D = − . V . The bottom left corner of the plot shows the on-state the device, while theupper right corner shows the off-state. (d) The magnitude of the drain current of the device along the dashed lines shownin (c). Individual gates [top gate for (i) and bottom gate for (ii)] do not provide an on-off ratio of more than 10 , but dual-gating [dashed line along (iii)] shows an on-off ratio of > × . (e) Schottky-like output characteristics of the FET withvarying V T G at a fixed positive back gate bias of 30 V. (f) Output characteristics of the device at a fixed negative V BG ,measured at 295 K, showing MOSFET-like characteristics. 14 M E F E vac E V E C Te NWMetal χ Te −3.5 0.0 3.5 7.0Top gate bias [V]10 −10 −8 −6 D r a i n c u rr e n t [ A ] V D = − 0.3V
50 100 q/k B T [V −1 ] −10 −8 −6 I D / T [ A / K ] V TG from 3 V to 7 V − − − − − − D r a i n c u rr e n t [ μ A ] V TG = -1 to 7 V T = 5 K (a) (b)(c) (d)
Figure 4: (a) Equilibrium band diagram of the device showing zero barrier to hole injection at the metal contact interface.(b) Transfer characteristics of the device at various temperatures (showing both forward and reverse sweeps), keeping theback gate floating. Off current and subthreshold swing reduce steeply with decreasing temperature, while the on currentincreases. The onset of ambipolar characteristics is observed at T = 5 K (blue trace). (c) Extracted activation energy forhole injection in the device as obtained from the slope of the Richardson plot. Inset: Richardson plot depicting the depen-dence of drain current on the temperature at various V T G and V D = − . V T G correspond to the positive slope of the Richardson plot, which is due to a increase in I D with a reduction in temperature,indicating non-thermionic carrier injection at the contact interface. (d) Output characteristics of the device at T = 5 K.15 e nanowire b
100 nm -10 -5 0 5 10-20-15-10-50 x y x [nm] y [ n m ] − M ob ilit y [ c m / V s ] T = 5 to 270 K Temperature [K]480600770100012251500 P ea k m ob ilit y [ c m / V s ] μ peak ∝ T −1.47 Scaled current [S]10 O n - o ff r a ti o
45 nm Needle like Te
13 nm This work O n - o ff r a ti o [34] [17] [34][51] [52][52] [16]This work[50][34] 2D Nanoflakes1D Nanowires (d)(c) (f)(e) (g) Figure 5: (a) Schematic cross-section of the nanowire device. (b) Scanning electron micrograph of the device cross-sectionwhen cut along the white dashed line in Fig. 3(b) and corresponds to the schematic in (a). (c) Hole mobility versus V T G at different temperatures, as extracted from the characteristics in Fig. 4(b). (d) Electrostatic potential contour lines andelectric field lines of Te nanowire device, as obtained from 2D FEM simulation. The simulation is run on the device cross-section. (e) Peak hole mobility plotted as a function of temperature. Mobility decreases from 1390 cm / V · s at 5 K to570 cm / V · s at 270 K. The dashed line shows a fit of the peak mobility as T − .47