Design Rules for High Performance Tunnel Transistors from 2D Materials
Hesameddin Ilatikhameneh, Gerhard Klimeck, Joerg Appenzeller, Rajib Rahman
11 Design Rules for High Performance TunnelTransistors from 2D Materials
Hesameddin Ilatikhameneh, Gerhard Klimeck, Joerg Appenzeller, and Rajib Rahman
I. A
BSTRACT
Tunneling field-effect transistors (TFETs) based on 2Dmaterials are promising steep sub-threshold swing (SS) devicesdue to their tight gate control. There are two major methodsto create the tunnel junction in these 2D TFETs: electricaland chemical doping. In this work, design guidelines for bothelectrically and chemically doped 2D TFETs are providedusing full band atomistic quantum transport simulations inconjunction with analytic modeling. Moreover, several 2DTFETs’ performance boosters such as strain, source doping,and equivalent oxide thickness (EOT) are studied. Later on,these performance boosters are analyzed within a novel figure-of-merit plot (i.e. constant ON-current plot).II. I
NTRODUCTION
Transistor scaling has driven device designs toward thinnerchannels for better gate control over the channel. 2D materialscan provide a shortcut to the ultimate channel thicknessscaling: an atomically thin channel. A tight gate control isimportant in FETs to obtain a 1-to-1 band movement in thechannel potential with respect to the gate voltage. The tightgate control is even more crucial for the performance of tunnelFETs (TFETs) [1], [2] since the scaling length and accordinglytunneling distance decreases with a better gate control [3]–[10]. The exponential dependence of the tunneling current onthe tunneling distance emphasizes the role of a thin channeland tight gate control in TFETs.Some 2D materials, such as graphene or silicene suffer fromthe lack of a bandgap ( E g ) and are not suitable for transistorapplications. On the other hand, 2D materials such as transitionmetal dichacogenides (TMD: MoS , WSe , MoTe , etc.) ex-hibit a sizable direct bandgap in their monolayer configuration.Among those, monolayer WTe shows particular promise forhigh performance TFET applications [4] due to its rather smalleffective mass and an expected bandgap of about 0.75eV [13].Note that a bandgap of about (1 . − . qV DD provides thebest performance in TFETs, where V DD is the supply voltage[11], which means that for a V DD of about 0.5V an E g range of 0.55-0.75eV is expected to provide best performance.Unfortunately, however, experiments indicate that the WTe
2H phase may not be stable [14].
This work was supported in part by the Center for Low Energy SystemsTechnology (LEAST), one of six centers of STARnet, a SemiconductorResearch Corporation program sponsored by MARCO and DARPA.The authors are with the Department of Electrical and Computer En-gineering, Purdue University, West Lafayette, IN, 47907 USA e-mail:[email protected]. (a) (b)
Fig. 1: Physical structure of a chemically doped (CD) (a) andelectrically doped (ED) (b) mono-layer WSe TFET with achannel length of 15nm and source and drain doping levels of1e20 cm − and no strain as default.This makes it essential to look for other methods for im-proving the performance of TMD TFETs utilizing the existingset of semiconducting TMDs. There are two major methodsto create the tunnel junction in these 2D TFETs: electrical[18], [19] and chemical doping [15]. The device structure ofa chemically doped (CD) and electrically doped (ED) TFETare shown in Fig. 1. In the case of CD-TFETs (Fig. 1a), thetunnel junction is created between a doped source region andthe electrostatically gated region. High doping of the sourceregion fixes the potential at the source side. Increasing the gatevoltage can reduce the potential in the channel and create inthis way a p-n like tunnel junction. In the case of ED-TFETs(Fig. 1b), n- and p-type potentials are defined by two gates atthe two sides of the tunnel junction and no chemical dopantsexist close to the tunnel junction. Avoiding chemical dopingin the tunnel region has several advantages. In particular, itavoids: 1) dopant fluctuations and threshold voltage shifts [23],2) dopant states within the bandgap which reduce the OFF-state performance [20], [21], and 3) the challenging task ofchemically doping 2D materials [22].In this work, different performance boosters for chemicallyand electrically doped 2D TFETs are discussed in detail. First,atomistic quantum transport simulations from NEMO5 tool[33]–[35] have been used to investigate the impact of strain,source doping level, and equivalent oxide thickness (EOT).Later on, an analytic model is used to explain the trends.III. S IMULATION METHOD
According to our previous analysis [4] WSe is the nextbest choice in terms of existing TMD materials for TFETapplications after WTe . Hence, monolayer WSe is chosen a r X i v : . [ c ond - m a t . m e s - h a ll ] M a r for our atomistic simulations and the detailed analysis ofvarious performance boosters. The WSe Hamiltonian em-ploys an sp d (cid:15) in and (cid:15) out )of WSe are different, the Poisson equation reads as follows[4] if the z direction is considered to be along the c-axis ofthe TMDs: ddx ( (cid:15) in dVdx ) + ddy ( (cid:15) in dVdy ) + ddz ( (cid:15) out dVdz ) = − ρ (1)where V and ρ are the electrostatic potential and total charge,respectively. The dielectric constant values ( (cid:15) in and (cid:15) out ) ofWSe are taken from ab-initio studies [24]. In this work,quantum transport simulations have been performed with oursimulation tool NEMO5 [33]–[35].IV. R ESULTS
In spite of the similarities between CD-TFETs and ED-TFETs, they obey rather different scaling rules and designguidelines [26], [29]. We will discuss the impact of the variousperformance boosters in CD-TFETs and ED-TFETs in thefollowing sections.
A. Chemically doped TMD TFETs
First, the design aspects of chemically doped (CD) TFETsare studied with the structure shown in Fig. 1a. A 15nm longmonolayer WSe channel with V DD of 0.5V is consideredFig. 2: Transfer characteristics of a chemically doped mono-layer WSe TFET with EOT=2nm (black curve), EOT=0.45nm(blue curve), doping level of 2e20 cm − (pink curve), andbiaxial strain of 3% (red curve). At each level, the previousboosting factor is included. Increasing the biaxial strain, andsource doping level and decreasing EOT boosts the ON-currentof 2D TFETs significantly. Fig. 3: SS as a function of drain-current I D for performanceboosted WSe CD-TFETs. Starting with EOT=2nm (blackcurve), EOT is then decreased to 0.45nm (blue curve). Sub-sequently, the doping level is increased to 2e20 cm − (pinkcurve), and finally a biaxial strain of 3% is applied (red curve).Notice that these performance boosters not only improve theON-current, but also they enhance the OFF-state performanceby decreasing SS and increasing I [36].in all CD-TFET simulations. We have identified a number ofcritical factors enhancing the performance of 2D CD-TFETs:strain, high doping levels of the source ( N D ), and small EOTvalues. Fig. 2 shows transfer characteristics of a WSe CD-TFET. The black current-voltage (I-V) curve shows the resultsfor the reference transistor with an EOT=2nm, N D =1e20cm − , and no strain. At the first step, EOT is decreased to0.45nm (blue curve). In the second step, the doping level isincreased to 2e20 cm − (pink curve), and finally a biaxialstrain of 3% is applied to WSe (red curve). The bandgap andFig. 4: Constant ON-current figure-of-merit. The blue linesshow a constant current for a set of device design parameters.The ON-current of TFETs mainly depends on the band bend-ing distance ( Λ ) and material properties of the channel m ∗ r and E g . The device design determines Λ which has two maincomponents: a) the depletion width of the source ( W D ) and b)the scaling length of the gated region ( λ ). Increasing dopingreduces W D , while decreasing the EOT, reduces λ . Both ofthese boosters result in a reduction in Λ . On the other hand,strain changes the material properties without affecting Λ . Fig. 5: Transfer characteristics of a WSe ED-TFET. Theimpact of spacing ( S ), oxide thickness, dielectric constant ofspacer ( (cid:15) S ), and strain is shown. The I-V of the referenceED-TFET with parameters S =5nm, t ox = t bot = t top =3nm and (cid:15) top = (cid:15) bot = (cid:15) S =20 is plotted (black curve). Then, S is reducedto 2nm (blue curve). Later on, t ox is reduced to 1.7nm (pinkcurve). Next, (cid:15) S is reduced to 1 (red curve). Finally, 3%biaxial strain is applied to WSe . The most important factorinfluencing the performance of the ED-TFET is (cid:15) S .effective mass of monolayer WSe decreases by applicationof biaxial strain; e.g. 3% biaxial strain reduces the reducedeffective mass m ∗ r and the band gap E g by about 10% and22%, respectively. Application of all performance boostersincreases I ON by more than 2 orders of magnitude.Fig. 3 shows the impact of the performance boosters (i.e.strain, source doping, and EOT) on the OFF-state performance.SS is plotted versus the drain current at which SS is calculated[28]. It is shown that the performance boosters not onlyincrease I ON , but also increase I (the current level whereSS=60 mV/dec [36]) and decrease SS. About 3 orders ofmagnitude increase in I and a factor of 3 reduction in SSare obtained combining the performance boosters.The ON-state performance of TFETs mainly depends on1) the band bending distance Λ (shown in Fig. 4) which isdetermined by the device design and 2) the channel materialproperties: m ∗ r and E g [26]. Fig. 4 shows a constant ON-current plot. Notice that I ON depends exponentially on theproduct of Λ and (cid:112) m ∗ r E g and since both axes are plottedon a logarithmic scale, constant current contours appear asparallel lines [27]. To achieve a higher I ON , one can reduce Λ or (cid:112) m ∗ r E g . In CD-TFETs, Λ is composed of two terms:1) the scaling length ( λ ) under the gated region and 2) thesource depletion width (W D ). Increasing the source dopinglevel, reduces W D , and reducing the EOT, reduces λ . Conse-quently Λ is also reduced. On the other hand, strain changesthe material properties without affecting Λ . Fig. 4 thereforeportrays the interplay between design and material parametersand the impact of the various performance boosters. B. Electrically doped TMD TFETs
In this part, the performance analysis of 2D electricallydoped (ED) TFETs is discussed. Notice that the design guide-lines for ED-TFETs are rather different due to the presenceof fringing fields. Fig. 1b shows the schematic of a doublegated ED-TFET [29]. In ED-TFETs, the tunnel junction is Fig. 6: The impact of spacing ( S ), oxide thickness ( t ox ), and (cid:15) of spacer ( (cid:15) S ) on the OFF-state performance of a WSe ED-TFET. Having small (cid:15) S and t ox are critical for a high I [36].created through two adjacent gates with opposite polarities.One of these 2 gates is a conventional gate and the other oneis connected to the source contact which tunes the electricallyinduced doping level of that side. Each gate has a length of12nm and V DS is set to 0.5V in all ED-TFET simulations. Themajor players affecting the performance of ED-TFETs are: 1)the spacing between the gates: S (Fig. 1b), 2) the thicknessof the oxide (not the EOT), 3) the dielectric constant of thespacing region ( (cid:15) S ) [32], and 4) strain. Fig. 5 shows that t ox and (cid:15) S have much higher impact on the performance of ED-TFETs compared to S and strain.Fig. 6 shows how the OFF-state performance of the 2DED-TFETs gets affected by different design parameters. It isFig. 7: a) The boundary conditions of the Poisson equation foran ED-TFET. b) The potential profile and Λ (white vectors)are both proportional to the total thickness of the device (i.e. Λ ∝ t bot + t top ) when the dielectric constants of the topand bottom oxides are equal ( (cid:15) bot = (cid:15) top ). This is often notachievable since 2D material channels are frequently built ona thick oxide. To overcome this problem one may also uselow dielectric constant materials for the back gate. c) When (cid:15) bot (cid:28) (cid:15) top the potential profile is dictated by the top gateand the back gate does not significantly impact the potentialprofile along the channel (i.e. Λ ∝ t top ). Fig. 8: Constant ON-current figure-of-merit for WSe ED-TFETs. The y-axis shows the impact of the bending distance Λ which has one main component: the scaling length of thegated region ( λ ). Notice that the expression for λ is different inED-TFETs if compared with CD-TFETs. Decreasing t ox , (cid:15) S ,and S reduces λ and Λ and increases I ON . If another materialwith smaller E g and m r (e.g. WTe ) is used instead of WSe ,the arrows would shift to the left and a higher ON-currentcould be achieved. This shows the importance of the choiceof materials for 2D TFETs.apparent that both SS and I significantly improve using athinner oxide, smaller spacing, and a smaller spacer dielectricconstant. The most effective improvement comes from asmaller spacer dielectric constant and thinner oxide whichincreases I by more than 4 orders of magnitude.One of the main differences between 2D CD-TFETs andED-TFETs is that the concept of EOT is not applicable toED-TFETs. In the case of ED-TFETs, the electric field atthe tunnel junction ( E T ) is inversely proportional to the totalthickness of the device (including top and bottom oxides)[29]–[31]: E T ∝ t top + t bot (2)This point is usually ignored in the design of electrically dopeddevices; a common layout uses a thick back oxide which leadsto a small E T . This problem can be overcome by using aback oxide with low dielectric constant compared to the topoxide ( (cid:15) bot (cid:28) (cid:15) top ). Fig. 7b shows the potential profile ofan electrically doped TFETs with thin and thick back oxideswith high-k dielectric on the top and bottom. It is apparent thata thick back oxide increases the potential spread and reduces E T . Fig. 7c shows that a low-k dielectric back gate can reducethe impact of thick back gate oxide significantly. Hence, E T ∝ t top (3)These results suggests that if a thin back oxide with gatesaligned with the top gates is experimentally challenging, onecan use a low-k back oxide to avoid performance degradationand enhance fabrication feasibility.There are two main differences between Λ of CD-TFETsand ED-TFETs: 1) the expression for the scaling length λ [29] and 2) λ replaces W D (Fig. 8). The constant I ON plot of theWSe ED-TFET is shown in Fig. 8.C
ONCLUSION
In conclusion, important design parameters of 2D CD- andED-TFETs are discussed here. It is shown that the EOT andsource doping ( N D ) are the main players in the case ofCD-TFETs, whereas the performance of ED-TFETs mainlydepends on t ox and (cid:15) S . Considering performance boosters canin principle increase the ON-current of both CD- and ED-TFETs by orders of magnitude.R EFERENCES[1] J. Appenzeller, Y.-M. Lin, J. Knoch, and Ph. Avouris, ”Band-to-bandtunneling in carbon nanotube field-effect transistors,”
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