Development of Readout Interconnections for the Si-W Calorimeter of SiD
M. Woods, R. G. Fields, B. Holbrook, R. L. Lander, A. Moskaleva, C. Neher, J. Pasner, M. Tripathi, J. E. Brau, R. E. Frey, D. Strom, M. Breidenbach, D. Freytag, G. Haller, R. Herbst, T. Nelson, S. Schier, B. Schumm
PPreprint typeset in JINST style - HYPER VERSION
Development of Readout Interconnections for theSi-W Calorimeter of SiD
M. Woods a ∗ , R. G. Fields a , B. Holbrook a , R. L. Lander a , A. Moskaleva a , C. Neher a ,J. Pasner a , M. Tripathi a , J. E. Brau b , R. E. Frey b , D. Strom b , M. Breidenbach c ,D. Freytag c , G. Haller c , R. Herbst c , T. Nelson c , S. Schier d and B. Schumm d a University of California, Davis,One Shields Ave, Davis CA 95616, USA b University of Oregon,Eugene, OR 97403, USA c SLAC National Accelerator Laboratory,Menlo Park, CA 94025, USA d University of California, Santa Cruz1156 High Street, Santa Cruz, CA 95064, USAE-mail: [email protected] A BSTRACT : The SiD collaboration is developing a Si-W sampling electromagnetic calorimeter,with anticipated application for the International Linear Collider. Assembling the modules for sucha detector will involve special bonding technologies for the interconnections, especially for attach-ing a silicon detector wafer to a flex cable readout bus. We review the interconnect technologiesinvolved, including oxidation removal processes, pad surface preparation, solder ball selection andplacement, and bond quality assurance. Our results show that solder ball bonding is a promisingtechnique for the Si-W ECAL, and unresolved issues are being addressed.K
EYWORDS : Detector design and construction technologies and materials; Hybrid detectors;Electronic detector readout concepts (solid-state). ∗ Corresponding author. a r X i v : . [ phy s i c s . i n s - d e t ] N ov ontents
1. Introduction 12. Bump Bonding Overview 2
3. Studies of Solders with Dummy Chips 54. Studies of Flex Cable Attachments 75. Discussion 10
1. Introduction
The International Linear Collider is a proposed e + e − collider designed for precision physics at theenergy frontier. The SiD concept, one of the two designs for particle detectors being designed anddeveloped, includes a Si-W electromagnetic tracking calorimeter [1]. It features a thin onion-skinconstruction of detection (silicon) and interaction (tungsten) layers, allowing for implementationof particle flow algorithms. In order to achieve both a minimum transverse size of electromagneticshowers and a sufficient number of radiation lengths, while maintaining a reasonable size for thedetector, thin layers are needed in the ECAL’s structure. The detection layer, including sensor andreadout hardware, is required to be no more than ∼ ∼ ∼
13 mm pixels. The sen-sors are read out by the KPiX chip, being developed at SLAC. The data readout bus consists of ahexagonally-stationed flexible kapton cable, which can handle up to sixteen KPiX chips. Currently,a version with a single station is used, as shown in Figure 1. Data transmission from the KPiX chipto the flex cable is accomplished via a set of short traces on the silicon sensor. Thus, the KPiX chipand the flex cable both need to be bonded to sets of pads on the silicon sensor. The bonding areaon the flex cable, termed the “tongue”, is shown in Figure 1. A closeup of the area of the siliconsensor that receives the flex cable is provided in Figure 2.Our previous work [3] investigated the use of gold stud bonding as the interconnect technology,but it had to be abandoned because the oxide layer beneath the bonding pads on the sensor waferwas unable to withstand from the high pressure of thermo-compression bonding. Bump bondingusing solder ball reflow offers the right solutions for bonding of both the KPiX and the flex cable tothe sensor wafer. In this paper, we report on the development of the solder bonding process for theSi-W ECAL. Most of the knowledge gained in this exercise is known to the interconnect industry– 1 – P i X Hex WaferFlex Cable
Figure 1.
An illustration of the assembly showing a flex cable before it is flipped and bonded to a hex wafer,which has a KPiX chip bonded on top (left). The cut-out window in the cable has two “tongues” with pads,that extend out and are bonded to the data-bus pads on the sensor wafer. A closeup of the tongue of the flexcable (right) details the layout of the traces coming from the kapton cable and the bond pads at the end of thetraces. The bonding pads on the flex cable for flex cable to hex wafer attachment measure 300 µ m × µ mwith a 500 µ m pitch; the longest tongue dimension measures 10.3 mm. but not widely disseminated, and had to be re-discovered for our custom application. At the UCDavis Facility for Interconnect Technology (UCD-FIT) [4], this research has evolved not from theviewpoint of an industrial engineer, but with the approach of an experimental physicist faced withproblems encountered in prototype development. Thus, we believe that the contents of this paperwill provide insight to those developing similar platforms for future HEP applications.
2. Bump Bonding Overview
The Hamamatsu silicon detector has 1024 bonding pads that connect via buried metal traces to eachof the 1024 pixel diodes on the sensor. The pads are to be bonded to matching pads on the KPiXchip, which form the inputs to individual channel amplifiers. An additional 64 pads on the KPiX,used to provide power, control signals and data output, are to be bonded to pads on traces leadingto the flex cable. The KPiX pads are squares 70 µ m on a side and form a rectangular grid with apitch of 200 µ m in the shorter dimension. Figure 3 shows a schematic representation of the flipchip bonding process required to establish mechanical and electrical connections and the layout ofthe pads and traces in the bonding region around the flex cable tongue. UCD-FIT houses a Finetech “Fineplacer pico ma” aligner-bonder which is a multipurpose diebonder with 5 µ m accuracy and repeatability [5]. A single camera views both the substrate (Si– 2 – igure 2. A close-up photograph of the silicon hex wafer, illustrating the layout of the bonding parts. The90 µ m × µ m bonding pads in the central array are placed on a 200 µ m × µ m grid. The pads for theflex cable attachment measure 300 µ m × µ m on a linear array of 500 µ m pitch. Hex pixels and the webof 2 µ m pixel-to-pad interconnect traces are also visible. Figure 3.
Cross-section of a bonded single station of a single layer the Si-W ECAL with abbreviated numberof pads. Solder balls (gray) placed on the KPiX chip and flex cable are bonded to the silicon sensor. Tonguesextending from the flex cable make contact with exposed pads on top of traces embedded in the siliconsensor. sensor) and package (KPiX) simultaneously using a rigid beam splitter. Engineered stability ofthe design guarantees that once the substrate material’s position and angle visually overlaps thatof the upper die, this orientation is maintained throughout the process of rotating the die withrespect to the substrate and bonding them. The other critical ability for the flip chip bonder is toensure coplanarity of the KPiX as it is brought into contact with the sensor wafer. Even an angulardiscrepancy of only 0.1 ◦ across the length of the KPiX chip will create a height difference of 35 µ m.The solder reflow process can be achieved in two ways: controlled gap and free-floating col-lapse. In the former, maintaining a minimum gap between the upper die and the lower wafer canensure a perfectly coplanar bonding scenario. Since the placement arm contains a heater (in addi-tion to the bottom heater in contact with the wafer) and always maintains contact with the KPiXchip, both items are also heated equally during reflow.– 3 –n alternative to the controlled gap is free floating solder bonding, in which the upper armreleases the die such that it rests on the lower wafer. This technique can be difficult with non-uniform solder ball heights. Also, the KPiX chip is heated from only the bottom and the heathas to travel to the KPiX pads via the solder balls themselves. Any gap between solder and paddue to height difference prevents proper heating. An elongated heating time causes the solder tomelt and allows its surface tension to pull the top chip into contact with more solder balls. At thispoint, the new physical contacts start heating their corresponding bonding pads and the attachmentproceeds. However, it is greatly preferred to have pads at or near the temperature of the moltensolder when contact is made. This may be achieved in a suitable reflow oven, but uniform heatingof buried solder balls is a challenge due to the absence of convection. Hence, the preferred methodfor reflow is to use the controlled gap technique with uniform heating of the flip chip assembly.Typically, a reducing chemical agent is used during bonding in order to remove oxides and/orprevent fresh oxidation. Pad preparation as a means to mitigate surface oxidation is discussed in thenext section; here, we describe the use of liquid flux or forming gas to reduce the tin oxide formedin the Pb/Sn solder. Early on, we used a non-viscous liquid flux that was well suited for permeatingthe area around our solder balls via brush application. While this procedure showed success, andusing liquid flux became our benchmark process, it was not desirable to have flux residue left overon the surface of sensitive chip electronics.A gas mixture of hydrogen (here, 5%) and nitrogen (95%) known as forming gas is capableof breaking down oxidation when the gas and samples are heated. Room temperature forminggas does little to prevent oxidation and its ability as a reducing agent is enhanced proportional tothe temperature of the materials at hand. Forming gas is typically used in reflow ovens and canprovide uniform oxidation removal without the need for a messy flux. We outfitted our flip chipbonder with custom baffling which could support a forming gas environment around the parts beingbonded. A study comparing the effectiveness of our liquid flux to the forming gas revealed that bothwere equally capable of removing and preventing oxide building up on the high temperature solder.Both methods resulted in multiple bonds with 100% yield and resistances in the few m Ω range. Useof liquid flux was discontinued after confirming the forming gas system’s effectiveness because itoffers uniformity, repeatability and a residue-free finish that cannot be readily achieved with themanual application of liquid flux. The solder bonding process begins with the creation of appropriate bonding surfaces. The layersof materials used to build up bonding pads play a vital role in successful long term bonding forelectrical components. Typically, silicon sensors and prototype ICs are fabricated with aluminumpads, which present a problem due to the presence of an insulating oxide layer which covers theentire aluminum surface. In technologies like gold stud bonding, ultrasonic ball placement breaksthrough the thin (few nm) aluminum oxide layer, but for solder reflow processes the aluminumoxide layer must be addressed.In the so-called electroless nickel immersion gold (ENIG) process, a zincate solution is used toremove aluminum oxide and deposit a zinc layer, which prepares the surface for electroless nickelplating. Immersion gold application follows to complete this process, providing a Au/Ni/Al metalstack. This is a preferred process for preparing solderable surfaces. The top layer of gold protects– 4 – igure 4. (Left) A photograph of dummy chips (Au/Ni/Al/Cr), developed for characterizing solder bondingtests. The smaller of the two chips is flipped and solder bonded on to the middle of the larger chip. (Right)A blow-up of the aluminum patterns. There are 20 sets of central pads for which 4-point resistance mea-surements of the bump bonds can be made. There are 40 sets of auxiliary pads, also bump bonded, whichare used for routing the traces to either end of the bump bonds. The numbers on the layout are enumeratingeach set of four measurement pads as they correspond to exactly one solder bond that can be measured forits resistance. the nickel layer from oxidation and dissolves into molten solder during bonding; a strong solderbond is formed with the nickel layer. The ENIG processing for our project was done at CVInc [6].In another technique, the metal stack can be built up by successive ion sputtering. The wafer iscoated with photo-resist and the windows are etched in the pad pattern. First, reactive-ion etching(argon ions) is performed in order to remove about 10-20 nm of top layer of the pads. This removesthe oxide layer and some part of the underlying aluminum. Next, a heavy metal like titanium,tungsten or platinum (or, their combination) is sputtered in order to form a barrier against migrationof lighter ions placed above this layer. This is followed by sputtering of nickel which forms thelayer that is wettable by solder. Finally, a thin layer of gold is deposited in order to protect thenickel from oxidation. The metal deposition for our dummy wafers (see below) was done in-housein the UCD micro fabrication facility. However, the processing of commercial chips was done atAdvanced Research Corporation [7], who have the capability to plasma etch the surface and sputterthe ions without breaking the chamber vacuum. Alternately, a similar stack of metal layers can bedeposited via electroplating. This technique requires patterning and etch-back of metal layers.
3. Studies of Solders with Dummy Chips
The assembly sequence for a single station module consists of first bonding the KPiX chip to thewafer and then bonding the flex cable, in two separate bonding runs. The two stage nature neces-sitates the use of two separate solders with sufficiently distant transition temperatures such that theKPiX attachment is not threatened by the second stage bonding. In order to study various solder– 5 – igure 5.
Bonding orientation and resistance measurement procedure for one pad set (not to scale). Thearrangement of the top (darker pads and traces) and bottom (lighter pads and traces) after bonding can beseen with a transparent top chip from directly over head (left). The three 125 µ m wide square bonding padscan be seen. The two on the lower portion serve only to allow current and voltage sensing to pass to the topchip. Only the resistance of the bond in the upper portion of the image is measured. A slant view (right)of the bonding scheme provides a glimpse of the bond and the (permutable) 4-point resistance measurementsetup. types, we designed and fabricated dummy chips, as shown in Figure 4. The bottom chip is largerwith traces leading to a pattern of 60 pads, each 125 µ m on a side. The top chip has a matchingpad pattern with traces interconnecting them to allow for loop back resistance measurements. Thiscombination allows us to make 4-point resistance measurements of 20 bump-bonds, while the other40 bonds, which transfer the resistance measurement’s current and voltage sense to and from theupper chip’s hidden traces, also contribute to yield measurements (Figure 5).To address the concern of heating the Si-W assembly through two different solder reflow steps,a series of tests were done using dummy chips. Two eutectic solders were selected for testing: ahigh temperature (melting point of 183 ◦ C) eutectic lead/tin solder (Pb 63%, Sn 37%) for theKPiX bond and a low temperature solder (melting point of 143 ◦ C) composed of indium/silver(In 97%, Ag 3%) for the flex cable. The KPiX chips manufactured by the Taiwan SemiconductorManufacturing Company (TSMC) come with the high temperature eutectic solder balls alreadyplaced on the pads. For our studies, solder balls of the two types were placed on the dummy chipsby CVInc.There was worry that a high temperature solder joint, bonded in the first stage of an attachment,would weaken and/or fail when brought near its melting temperature during the second stage. Todetermine the effect of this temperature cycling, a pair of dummy chips was bonded using hightemperature solder (at 210 ◦ C) and the resistances of the bond were measured. These values areshown in blue in Figure 6, left, where each of the twenty measured pads is shown. The maximumresistance seen is 10 m Ω , which is acceptable for the application.The pair of bonded chips was then cycled up to 160 ◦ C, which is the temperature that is usedfor bonding the low temperature solder. Afterward, the same 4-point resistances were measured.The yellow bars in Figure 6 show the resistance of the sample after reheating. The resistances haveall decreased to a range of 1-3 m Ω . This lowering may be explained as due to domain walls of non-– 6 – W R r e s i s t a n c e o f s o l d e r j o i n t ( m Ω ) Temperature cycled resistance of SnPb solder bondsInitial bond: 210 ◦ CReheated: 160 ◦ C W R r e s i s t a n c e o f s o l d e r j o i n t ( m Ω ) Temperature cycled resistance of InAg solder bonds
Figure 6.
Results from temperature cycling two kinds of solder. The left figure shows bond resistances ofthe high temperature SnPb solder (melting point 183 ◦ C) after bonding at 210 ◦ C, as well as the same solderrecycled through the low temperature solder’s bonding temperature. On the right is a plot showing that InAglow temperature solder (melting point 143 ◦ C) can be taken to 210 ◦ C before bonding and still produceresistances far under one ohm. Results are typical. The plot on the right is necessary only if the InAg solderis placed on the silicon sensor before bonding, not the flex cable. Both illustrate that no harm in cycling thesolder is seen. uniform alloys in the solder shifting and decreasing electrical resistance. Clearly the resistancesdid not increase with the temperature cycle and thus this bonding scenario is acceptable.If placed on the silicon sensor, the low temperature solder will also be reflowed during thebonding of the KPiX chip, but with nothing attached. Using dummy chips with low temperaturesolder, we first cycled the chip to a temperature of 210 ◦ C to imitate the high temperature solderbond; the chip was not being bonded at this high temperature, but rather simply exposed to thehigh temperature. Following this high temperature exposure, the sample was cooled and thenbonded to its mating dummy chip at the usual 160 ◦ C. Figure 6, right, shows the 4-point resistancemeasurements following this bonding process. Each of the twenty pads is within an acceptablerange. The highest value of 24 m Ω does not cause concern as it is still much smaller than one ohm,which is our acceptance level.
4. Studies of Flex Cable Attachments
After tests conducted using the dummy flip-chip components concluded that no negative effectswere seen with the chosen types of solder, we initiated trials of flex cable attachment using thelow temperature solder. Because the silicon sensors are very expensive, we continued with use ofdummy silicon sensors that allowed nearly identical bonding conditions without the financial risk.A new dummy hex wafer was fabricated to facilitate these studies, as shown in Figure 7.Low temperature solder balls were placed by CVInc on the dummy sensor (and later the flexcable). After aligning the two components they were taken through the “standard” heating profile.The silicon dummy sensor and the kapton flex cable were brought up to a bonding temperature of163 ◦ C over twenty seconds. The setup plateaus at this temperature for ten seconds before graduallycooling down over several minutes using forced air cooling.– 7 – igure 7.
Photographs of the dummy hex silicon wafer, which shares the same dimensions as the actualHamamatsu sensors. Probe pads connecting to the cable bond pads are placed in the centre. On the right isa close-up showing solder balls placed on pads that will receive the flex cable.
Figure 8.
A photograph of the flex cable showing strain relief slots added in critical areas. The slots nearthe center of the hexagonal portion of the flex cable help mitigate stress applied to the silicon sensor bondingpads. The slots near the edges of the flex cable are relieving the stress on guard ring pads. Texture due toburied trace routing is revealed in the reflection.
It was found that good solder bonds were made between the pads of the dummy silicon sensorand one end of the flex cable. However, due to the difference in coefficients of thermal expansion(CTE) between the silicon and the kapton, the solder joints at the other end were ripped off uponcooling. The CTE for the silicon hex wafer (or dummy chip as the case may be) is 2.6 ppm/ ◦ Cwhile the CTE for kapton polyimide is 20.0 ppm/ ◦ C. The difference of 17.4 ppm/ ◦ C in CTE acrossthe 3 cm gap between the tongues of the flex cable for a temperature difference of 137 ◦ C seenduring bonding produces a difference in expansion of 72 microns, a distance coincidentally closeto the diameter of the solder balls. – 8 – igure 9.
Cross section of the flex cable bonding concerns and procedures. On the left, the dangers invariable kapton tongue bending are shown. The black and white outlines show upward tongue bendingleaving a gap above the 160 µ m solder ball, creating an open bond and a low tongue that would significantlycompress molten solder and risk solder bridging bonding sites and shorting pads together, respectively. Onthe right, the arm of the flip chip bonder bringing a heat spreader into contact with kapton tape above thetongues, pinching the tongues at an appropriate height with the surrounding cable thickness as a guide. Strain relief slots were cut into the flex cable to ameliorate this problem, as shown in Figure 8.The largest section of empty space between the two tongues is present to clear the KPiX chip, notto provide CTE mismatch relief. With slotting in place, temperature cycling could be performedwithout tearing traces off of silicon or shearing any solder away from bonding pads.Controlled gap reflow of the solder became an issue due to an unforeseen characteristic of thekapton tongues. Due to the flexible nature of the cable and internal stresses in the material leftover from fabrication, the tongues see an unpredictable change in bend angle during heating. Stepswere needed to ensure that the bonding pad at the end of the tongue was present at the correctheight above the hex wafer which was arbitrarily chosen as 60% of the 160 µ m solder ball height;failure to control the bending could cause open circuits if the tongue was too high or short circuitingbetween bonds if the solder was violently compressed beyond individual pads and overflowing thesolder dam structures in the cable if the tongue was too low (Figure 9 (left)).Compensation for the tongue bending required mechanical compensation to position the tongue.Because the conducting layer in the flex cable is located near the middle of the kapton cable’s struc-ture, surface material is removed to gain access to the conductive pads leading to a tongue that isthinner than the surrounding cable. We introduced thin strips of kapton tape underneath the tonguejust next to the bonding pads and then above the tongue directly above the bonding pads as seen inFigure 9 (right). The combined thickness of the two pieces of tape and the tongue was designed toequal the overall cable thickness. The kapton tape used was 4 mil thick for this solder ball. Only asingle layer above and below was applied to provide sufficient stand-off.During bonding, a heat spreader that could encompass both tongues and wide enough to layon the thicker areas of the flex cable was used to compress the assembly until the heat spreaderwas flush with the cable. The kapton standoffs corrected for excessive bending which allowed usto make viable solder bonds to the dummy hex wafer. With these issues under control, the flexcable to dummy hex wafer bond produced no open bonds, no shorts between pads, and reasonablesub-ohm resistance measurements. – 9 – . Discussion Various solder reflow bump bonding tests have established this process as suitable for the inter-connects required in the assembly of the Si-W calorimeter. The use of two types of solders withdifferent melting points has been proven as a successful method for sequential bump bonding onthe same substrate. An appropriate metal stack for solder bump bonding has been established. Aflex cable designed with carefully placed strain-relief slots has been successfully bonded to siliconwafers without any detachment occurring upon cool down. These results should provide importantinput to future designs involving interconnections between silicon chips and flex cables.The preparation of pad surfaces for the hexagonal wafers produced by Hamamatsu [8] is prov-ing to be a challenge. They were treated by CVInc for the ENIG process but the zincating processfailed to produce a plating layer. An attempt to build up a metal stack of Au/Ni/Ti via a sputteringprocess was attempted by ARC. However, the stack detached during lift-off, leaving the originalsurface behind. We are investigating the surface composition of the pads in order to understandthe cause, while also pursuing a plating and etch-back technique with Fraunhofer IZM [9]. We donot understand whether there are deficiencies in the metallization techniques or whether the padsurface of the Hamamatsu detectors is anomalous. Flip-chip bonding of ASICs to commercial alu-minum substrate pads is a well-developed process. We can expect eventually to find the source ofour problem, be it the Hamamatsu pads or our processing, and make successful bonds of the ASICto the sensor wafer. If the problem is the former, we will need to have Hamamatsu fabricate newwafers with gold pads. In summary, while there are remaining issues with sensor pad surface, theinterconnect issues have all been solved.
Acknowledgments
This work is funded by the Linear Collider Detector R&D Program, sponsored by the DOE Officeof Science. We thank Steve Ellison (ARC) and Terence Collier (CVInc) for numerous technicaldiscussions.
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