Efficient charge modulation in ultrathin LaAlO 3 -SrTiO 3 field-effect transistors
A.E.M. Smink, B. Prabowo, B. Stadhouder, N. Gauquelin, J. Schmitz, H. Hilgenkamp, W.G. van der Wiel
EEfficient charge modulation in ultrathin LaAlO -SrTiO field-effecttransistors A.E.M. Smink, B. Prabowo, B. Stadhouder, N. Gauquelin,
1, 2
J. Schmitz, H. Hilgenkamp, and W.G. van derWiel MESA+ Institute for Nanotechnology, University of Twente, P.O. Box 217, 7500 AE Enschede,The Netherlands EMAT, University of Antwerp, Groenenborgerlaan 171, 2020 Antwerp, Belgium (Dated: September 30, 2019)
At the LaAlO -SrTiO interface, electronic phase transitions can be triggered by modulation of the charge carrierdensity, making this system an excellent prospect for the realization of versatile electronic devices. Here, we reportrepeatable transistor operation in locally gated LaAlO -SrTiO field-effect devices of which the LaAlO dielectric isonly four unit cells thin, the critical thickness for conduction at this interface. This extremely thin dielectric allowsa very efficient charge modulation of ∼ . × cm − within a gate-voltage window of ± thickness, we observe a negligible gate leakagecurrent, which we ascribe to the extension of the conducting states into the SrTiO substrate.Charge modulation in field-effect transistors (FETs) is thecore physical mechanism enabling modern-day electronics. Ina standard semiconductor such as silicon, its main purposeis to change the electrical conductivity, defining the “0” and“1” states in digital electronics. In other classes of materi-als, e.g., transition metal dichalcogenides and complex oxides,tuning the charge carrier density can trigger quantum phasetransitions, offering possibilities for fundamental studies andfor using such transitions in electronic devices . However,these transitions mostly take place at very high charge carrierdensities, exceeding 10 cm − . Significant tuning of such ahigh charge carrier densities can only be achieved by meansof chemical doping techniques and electrolyte gating, whichare both impractical for functional devices.In doped strontium titanate (SrTiO ) and at the conductinginterface between SrTiO and selected other insulators suchas LaAlO , (super)conducting and insulating phases are neareach other in terms of charge carrier density , typically inthe range of a few times 10 cm − . In the interface case,the geometry is intrinsically the same as the semiconductor-oxide stack of a metal-oxide-semiconductor FET (MOSFET),making such interfaces appealing for use in field-effect de-vices. Moreover, at low temperatures the SrTiO substratecan also be used as a gate dielectric (backgating), owing to itshuge permittivity . For the archetypical LaAlO -SrTiO inter-face, reports on the significant field-effect tuning of the criti-cal temperature for superconductivity , the considerable low-temperature mobility , and of spin-orbit coupling strength showed the versatility of this system both for fundamentalstudies and for its possible use in future electronics.However, backgating takes place over large areas and re-quires the application of voltages in the order of 100 Vacross the typically 0.5-mm-thick SrTiO substrate to achievea carrier density modulation of up to ∼ × cm − electrostatically . Hence, the backgating geometry is unsuit-able for integration into circuits, which requires local opera-tion by voltages of ∼ -SrTiO interface, where the volt-age is applied across the LaAlO layer, is challenging because structuring these materials into (small) channels is not a trivialprocess . Low-voltage, topgate FETs were first realized byFörg and coworkers , after which the functionality of suchdevices was extended greatly . Unfortunately, the emer-gence of gate leakage currents across the thin LaAlO layer– typically 8 to 20 unit cells (uc) thick – limited the chargemodulation to about 2 × cm − . In parallel, the capabil-ity of achieving extreme charge modulations in SrTiO -basedFETs, up to a record value of 2 . × cm − , was demon-strated in inverted structures with a thick SrTiO layer as thedielectric . Still, these devices have thick dielectrics and ahigh intrinsic carrier density, compromising low-voltage andlocal operation. The ultimate oxide-based FET, in which asmall gate voltage achieves a charge modulation of severaltimes 10 cm − , possibly enabling local switching of quan-tum phase transitions, therefore has remained elusive.In this Letter, we demonstrate such efficient charge modula-tion in Au-LaAlO -SrTiO FETs in which the LaAlO dielec-tric has a nominal thickness of only four unit cells (uc), thecritical thickness for interface conduction . The devices dis-play repeatable transistor behavior with low leakage currentsand high ON/OFF ratios. Capacitance-voltage measurementsreveal a large voltage-independent contribution to the capac-itance, and a low effective permittivity for the LaAlO layer.The latter can be ascribed to a dielectric ‘dead layer’ formingon the Au-LaAlO interface, as indicated by scanning trans-mission electron microscopy. Despite this layer, the chargemodulation is very efficient with a high capacitance per unitarea, proving the principle of low voltage modulation of highcharge densities in complex-oxide based FETs.The fabrication of our devices started with a standard pro-cedure to terminate the SrTiO substrate on the TiO sites ofthe (001) surface plane . To enable structuring of the LaAlO film into channels, we deposited an AlO x layer at room tem-perature, which was etched in OPD4262 developer used forUV lithography . The subsequent growth of LaAlO and Auby pulsed laser deposition (PLD) was done in situ , ensuringthe interface between these layers to be as clean as possi-ble. The LaAlO was deposited in an O process pressure a r X i v : . [ c ond - m a t . m e s - h a ll ] S e p LaAlO SrTiO Au ‘dead layer’ (a) Au/TiSource Au/TiDrainAlO x AlO x LaAlO Au topgate
LaAlO (b) [001][010] Figure 1. (a) High-Angle Annular Dark Field (HAADF) ScanningTransmission Electron Microscopy (STEM) image taken along the[100] direction of a SrTiO -LaAlO -Au stack. (b) Scanning ElectronMicrograph (SEM) of a FET with width, W = µ m and length, L = µ m, and indications of the source, drain and (top)gate contacts. of 1 × − mbar at T = ◦ C, with a laser fluence of 1.3 Jcm − , spot size of 2 mm and a frequency of 1 Hz, resulting ina growth rate of one uc per ∼
20 pulses, monitored by reflec-tive high-energy electron diffraction (RHEED). The distancebetween the substrate and the single-crystalline target was 45mm. After the LaAlO deposition, the sample was annealedfor 1 h in an O pressure of 400 mbar at a temperature of 600 ◦ C. Then, the Au was deposited in an Ar process pressure of0.22 mbar, at T = ◦ C with a laser fluence of 3.6 J cm − and a spot size of 1 mm . To reduce the energy of the parti-cles arriving at the substrate, the target-substrate distance wasincreased to 60 mm. This way, a layer of ∼
30 nm was grownafter 9000 pulses at f = , which were structured bylift-off. Finally, the gate electrode was patterned using UVlithography and structured using a buffered KI solution .In the dc current-voltage measurements, the drain current, I D , was measured by a Keithley 2401 source-measure unit thatalso provided the drain-source voltage, V DS . The gate current, I G , was determined by measuring the voltage over a 1 k Ω resistor using a Keithley 2000 multimeter. The capacitance-voltage characteristics were measured with a Keithley 4200-SCS parameter analyzer with a 4210 capacitance-voltage unit,using an ac voltage of 25 mV and a frequency of 10 kHz: closeto the optimal frequency of ∼
30 kHz for these devices . Allmeasurements were performed at room temperature with thesource terminal connected to ground.Figure 1 presents electron microscopy images of two of ourdevices. In the cross-sectional image (Fig. 1(a)), four unitcells of LaAlO are clearly visible. Like previously reportedby another group , we also observe a thin disordered layerbetween the LaAlO and Au layer with a thickness of ∼ . -SrTiO FET like the one shown in Fig. 1(b), -1 0 1 2 3 4 5-10-50510152025 -2 -1 0 1 210 -3 -2 -1 I D ( A ) V DS (V) V GS (V) -1.5 +2.0 -1.0 0.0 +1.0 (a) V DS (V) +0.1 +0.2 +0.5 +1.0 +2.0 +5.0 I D ( A ) V GS (V)(b) |I G | Figure 2. Current-voltage characteristics of device A. (a) Drain cur-rent, I D , versus drain-source voltage, V DS , with 250-mV steps in thegate-source voltage, V GS . The open symbols separate the ohmic andsaturation regimes for each V GS . (b) Transfer curves for varying V DS ,and the gate current (dashed line) for V DS = with a 4-uc-thin dielectric and channel length, L , and width, W , both equal to 10 µ m. We measured over ten devices ontwo different samples, with varying channel dimensions. Allof these devices displayed transistor behavior, with ON/OFFratios between 10 and 10 . In Fig. 2(a), we observe clearohmic (triode/linear) and saturation (active) regimes. The cir-cles separating these regimes represent the saturation voltageand current, which both increase monotonously with V GS . Forhigher gate voltages, the saturation current does not followthe expected quadratic trend anymore , which we ascribe toa suppression of carrier mobility with increasing topgate volt-age as previously observed .In Figure 2(b), switching of the channel conductivity isclearly demonstrated for all V DS , from which we extract thetransfer characteristics of this device. From a linear fit to √ I D versus V GS , we determine the threshold voltage, V th , at − . ± .
01 V. The subthreshold swing of 98 ± V th , thus is not strictly sub threshold – and the maximum ON/OFF ratio of ∼ for V DS = + . Note that theON/OFF ratio is limited by a finite OFF current, caused by a(minute) gate current emerging below V GS = − . C ( V ) characteristic to semiconductor-based devices is that below threshold, the capacitance re-mains constant, instead of increasing due to the formation ofan accumulation region . This voltage-independent capaci-tance at negative gate voltage is observed commonly in metal-LaAlO -SrTiO junctions and is generally ascribed toa voltage-driven metal-insulator transition (MIT) . Whencomparing this curve to Fig. 2(c), we find that the voltage-independent and voltage-dependent regions are separated bythe threshold voltage of − .
81 V. C c C s g GS R GateSource (a) (b)(d)(c)
GGSS DDON ( V GS > V th )OFF ( V GS < V th ) Figure 3. Capacitance of Au-LaAlO -SrTiO FETs. (a) Equiva-lent circuit for the gate-source connection of a FET. The gate-sourcecapacitance C GS ( V GS ) is modeled as a voltage-dependent element, C c ( V GS ) in parallel to a voltage-independent component, C s . (b)Capacitance-voltage characteristic of device A, with indications ofthe threshold voltage, V th , C c , and C s . (c) Illustration of the electricfield lines in the device contributing to the stray (blue) and channel(red) capacitance, above (top panel) and below (bottom) threshold.(d) Scaling of capacitance with channel width, W , for devices with L = W . Dashed lines are power-law fits to the data for C c and C s . For a quantitative analysis, we assume that the voltage-independent, or ‘stray’, capacitance, C s , is a parallel elementto the capacitance between the gate and the conducting chan-nel, C c , yielding C GS ( V GS ) = C s + C c ( V GS ) . To substantiatethis assumption, we measured the capacitance-voltage char-acteristics of several devices with varying dimensions. Thisallows to extract the scaling of gate-source capacitance withdevice area, as depicted in Figure 3(d). Here, we considerdevices with a square channel, i.e. L = W , and extract thecapacitances C GS and C c at V GS = + . W , but that C s and C c do. The channel capacitancescales with device area ( L × W ), in excellent agreement with aparallel-plate capacitor model. Hence, we can extract the ef-fective relative permittivity, ε r ≈ . ± .
4, using d = . /
3, thus depends on the geometry in a nontrivial way.To our knowledge, there is no theory yet that explains such adependence on the device geometry. Extrapolation of our datasuggests a crossover to occur at L = W ≈ . µ m, implyingthat the stray capacitance becomes dominant in small devices.We postulate that this large stray capacitance is due to thevery large permittivity of the channel material, SrTiO , whichis ∼
300 at room temperature . As illustrated by the blue lines in Fig. 3(c), the gate terminal is capacitively coupled to thesource and the drain through an electric field. The capacitanceassociated with this electric field depends on the permittivityof the insulator and of the channel material. In most materials,this would not be very significant; here, the very high permit-tivity of the channel material implies that the gate-source ca-pacitance in absence of a conducting channel remains sizable.To obtain the modulation of charge density in the channel,we omit the stray capacitance and integrate C c with respect to V GS . Between threshold and + . × cm − . Above + + ∼ . × cm − . The gate voltagerequired for this modulation does not exceed + , which has ε r = .
9. Using ε r ≈ . ± . d = . . ± . ε r is much lower than ones reported inliterature for thick LaAlO films , which range from 18to 30. This suppression of ε r in metal-LaAlO -SrTiO junc-tions is a widely observed phenomenon ; with increas-ing LaAlO layer thickness, ε r was reported to approach thebulk value . This was ascribed to a ‘dead layer’ forming in-side the LaAlO film because of structural interface effects .Because Fig. 1(a) shows a disordered layer forming on topof the fully intact, 4-uc-thin LaAlO layer, we propose an al-ternative scenario in which the ‘dead layer’ forms on top ofthe LaAlO rather than inside it. A series capacitor model inthis scenario is mathematically equivalent to the one used byHosoda et al. : d LAO + d dead ε r,tot = d LAO ε r, LAO + d dead ε r,dead . (1)By using ε r, LAO = d LAO = .
52 nm, and d dead = . ε r,dead ≈ . ± .
3, which we deem a reasonable valuefor a disordered layer. Therefore, this disordered layer at theLaAlO -Au interface poses a viable alternative scenario to thedead layer within the LaAlO film; further investigations ondevices with varying LaAlO layer thickness made using dif-ferent fabrication procedures may distinguish between thesetwo possibilities.Despite the suppression of ε r , the charge modulation inour devices is efficient and not compromised by gate leak-age currents. Moreover, in comparison to previous reportson Au-LaAlO -SrTiO stacks with 4-uc-thin barriers, wherethe gate current was used to perform tunneling spectroscopyof the interface , the gate current density is about fourorders of magnitude smaller. To investigate the factors deter-mining the gate leakage current, we carried out temperature-dependent measurements as described in the SupplementaryInformation. The results show that ohmic and hopping-basedconduction are negligible, and that the gate current is dom- -2 -1 0 1 210 -3 -2 -1 -4 -3 -2 -1 -4 -2 0 2 410 -3 -2 -1 I D ( A ) V GS (V) Cycles 10 50 100 200 500 1000 (a) | I G | ( A ) V GS (V)(b) (c) | I G | ( A ) V GS (V) Figure 4. (a) Response of the transfer curve of device B ( L = W = µ m) to repeated gate voltage cycling between V GS = − . + V DS = + V GS upwards (downwards). (b) Gate current of device B during therepeated cycling in (a), for V DS = L = W = µ m) upon sweeping the gate voltage to ± V DS = inated by direct tunneling and Schottky emission. Accord-ingly, the density of defects inside the LaAlO layer must bevery low and memristive effects based on the movement ofdefects should be absent. To confirm this, we measured thedevice response against repeated gate voltage cycling and upto high gate voltages of ± ∼ × , in good agreement with previous results .To explain the surprisingly large difference in gate cur-rent between the tunneling spectroscopy devices of Refs.24, 35, 36 and our FETs, we consider the factors determiningdirect tunneling currents. Since both types of devices havethe same material stack with the same thicknesses and the‘dead layer’ is present in the tunneling spectroscopy studies as well, the energy landscape in terms of barriers and thick-ness should be the same. Therefore, we argue that the out-of-plane distribution of mobile charges in the SrTiO differsgreatly between the two types of devices, increasing or de-creasing the effective barrier thickness. In SrTiO , the mobilecharges do not reside exactly at the surface, but are distributedwithin a quantum well . This charge distribution dependscrucially on the electrostatic boundary conditions for the well,which are highly susceptible to the environment in which theLaAlO film is grown . In consequence, samples grown indifferent conditions have varying charge distributions in thequantum well. Especially for samples with thin LaAlO lay-ers, the effective depth at which the mobile charges reside canthus vary greatly among samples grown under different con-ditions. We note that this effect may be enhanced greatly by arecently proposed region of negative polarization directly onthe SrTiO side of the interface . Of great importance for de-vice operation is that this effective thickness increase shouldnot suppress the capacitance by much, for the permittivity ofSrTiO exceeds 300 even at room temperature . Hence, wepropose that this increase of the effective tunnel barrier thick-ness, without lowering the capacitance, is the key enabler ofthe efficient charge modulation observed in our devices. In summary, we characterized the operation of Au-LaAlO -SrTiO field-effect transistors with a LaAlO layer thicknessof only four unit cells, or 1.5 nm. Our devices exhibit highlyrepeatable transistor behavior with very low gate leakage cur-rents. In capacitance-voltage measurements, the gate-sourcecapacitance becomes voltage-independent below threshold,which we attribute to stray fields coupling the gate to thesource and drain terminals in absence of a conducting chan-nel. Integration of the voltage-dependent part of the capaci-tance yields a charge modulation of about 3 . × cm − ,within a gate voltage range of ± layers grown on SrTiO . Scanning transmission elec-tron microscopy imaging suggests that this suppression is dueto a dielectric ‘dead layer’ forming at the Au-LaAlO inter-face, with a thickness of ∼ . channel.Because of the high dielectric permittivity of SrTiO , this doesnot significantly affect the gate-source capacitance, enablingefficient modulation of high charge densities by low gate volt-ages without excessive gate leakage currents. We foresee thatmaking use of this delocalization in quantum wells opens newvenues to engineer high-charge-density field-effect transistorsbased on advanced materials. ACKNOWLEDGMENTS
We thank Maurits de Jong for his help with the capacitance-voltage measurements, Jochen Mannhart and Hans Boschkerfor stimulating discussions, and Frank Roesthuis, Dick Veld-huis, and Thijs Bolhuis for technical assistance. We acknowl-edge financial support through the DESCO program of theFoundation for Fundamental Research on Matter (FOM), as-sociated with the Netherlands Organization for Scientific Re-search (NWO).
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