Evaluation of Radiation Hardness of High-Voltage Silicon Vertical JFETs
PPrepared for submission to JINST
Evaluation of Radiation Hardness of High-Voltage SiliconVertical JFETs
Gabriele Giacomini, a , Marco Bomben b Wei Chen, a David Lynn, a a Brookhaven National Laboratory, Upton, 11973, NY, USA b LPNHE, 4 Place Jussieu, 75005 Paris, France
E-mail: [email protected]
Abstract: In the future ATLAS Inner Tracker, each silicon strip module will be equipped with aswitch able to separate the high voltage supply from the sensor in case the latter becomes faulty.The switch, placed in between the HV supply and the sensor, needs to sustain a high voltage inits OFF state, to offer a low resistance path for the sensor leakage current in the ON state, and beradiation hard up to 1 . · n eq / cm along with other requirements. While GaN JFETs havebeen selected as suitable rad-hard switch, a silicon vertical HV-JFET was developed by BrookhavenNational Laboratory as an alternative option. Pre-irradiation results showed the functionality of thedevice and proved that the silicon HV-JFET satisfied the pre-irradiation requirements for the switch.To assess its suitability after irradiation, a few p -type HV-JFETs have been neutron irradiated atJozef Stefan Institute (JSI, Ljubljana, Slovenia). This paper reports the static characterization ofthese irradiated devices and the TCAD numerical simulations used to get an insight of the physicsgoverning the post-irradiation behaviour.Keywords: Radiation-hard electronics, Detector control systems, Modular electronics Corresponding author. a r X i v : . [ phy s i c s . i n s - d e t ] J u l ontents At the High-Luminosity Large Hadron Collider (HL-LHC) at CERN (Geneve, Switzerland), theATLAS experiment will run with a completely renovated Inner Tracker (ITk) with respect to itsLHC phase [1]. One of the differences in this upgrade is that currently either three or four siliconmicrostrip sensors will be biased by a single common High-Voltage (HV) line. If one of these threeor four sensors fails and starts drawing a high current, all the other good detectors connected to thesame HV line must be switched off, thus losing a large detector area. To avoid this situation thefaulty detector must be disconnected from the common HV line. The solution is to place a switchbetween each strip sensor and the common HV line. Normally the switch is closed (ON State)which means that a little voltage falls on it and almost the full voltage is applied to the sensor whilethe sensor leakage current flows through the switch. If the sensor gets damaged then the switch isopened (OFF state) and the full voltage falls on the switch. There is little or no current from thefaulty sensor which is kept at about zero voltage but the remaining good devices connected to thesame HV line continue working normally. The requirements for such a switch so that it can beusable in the ITk are:• in the OFF state, capable of operating above 600 V (with an equivalent source-drain resistanceR ds , OFF >
100 M Ω );• in the ON state, having a R ds , ON < − Ω ;• capable of operating in a 2T magnetic field;• survive radiation doses of 50 Mrad and fluences of 1 . · n eq / cm .These requirements exclude, among others, electro-mechanical switches (which suffer in highmagnetic fields), power MOSFETs (since their threshold voltage V th changes with irradiation) andpower transistors (their gain changes with irradiation). A program, called HV-Mux was initiatedto seek after such a switch [2]. Silicon carbide and gallium nitride JFETs have been extensively– 1 – igure 1 . Microscope picture of a quarter of a HV-JFET, showing the positions of the gate and source in thedevice, while the drain is the back contact itself. The picture shows an area approximately 0.5 mm x 0.5 mmlarge. investigated by means of irradiation campaigns. The latter satisfies all the specifications listedabove and has been selected be used as the switch for the ITk. However, prior to establishing itssuitability, we at Brookhaven National Laboratory (BNL) we developed a new kind of HV siliconJFET which satisfies most of these requirements before being irradiated. To assess its suitability asa rad-hard switch at the fluence expected at the ITk, some p -type samples were neutron irradiated atthe TRIGA nuclear reactor run by the Jozef Stefan Institute (JSI, Ljubljana, Slovenia). The fluencesat which the JFETs were exposed were: 4 · , 8 · and 1 . · eq / cm .This paper is organized as follows: a brief description of the device and its functioning ispresented in Section 2. The results, consisting in a static characterization at the probe station, areshown in Section 3. TCAD numerical simulations that have been performed to get an insight of thephysics governing the irradiated devices are presented in Section 4. Figure 1 shows a microscope picture of a typical HV-JFET used in this study. It has been fabricatedon 4", p -type epitaxial wafers. The thickness of the epitaxial layer is 50 µ m, which has been grownover a thick handling wafer. The doping concentration of the epitaxial layer is 7 · cm − resultingin a full depletion voltage of 130 V as measured on large-area diodes present as test structures onthe wafer. We expect a decrease of the substrate full depletion voltage after irradiation, even afterthe highest fluence used in this study (1 . · eq / cm ): as reported in [3], in fact, weexpect a decrease of the effective doping concentration, due to acceptor removal (boron) for all thefluences used. Figure 2 shows the cross section of a simplified device, as used for all the TCADnumerical simulations of Section 4. On the top side of the device, the source surrounds the topgate. In the actual devices fabricated in our clean room, to increase the width of the device, andproportionally its current in the ON state, the source and the top gate are designed in an interdigitated– 2 – igure 2 . Cross sectional view of a typical HV-JFET. This geometry has been used in all the TCADsimulations of Section 4. The structure is symmetric with respect to the vertical axis X=0. configuration: the source fingers are shorted together by the metal layer and so are the top gatefingers. The total width of the device is about 20 cm. The bottom gate runs all over the active area(about 1 mm x 1 mm in the production) but features a gap of a few microns just below the middle ofthe top gate. The top gate is shorted through a deep implant with the bottom gate, so that the JFETsare in a triode configuration, but this results in it not being possible to independently bias the twogates in this first prototyping fabrication. As in a usual JFET, the channel runs all over the surfaceas well, connecting all the source implants together. Its length is defined by the overlap between thegates. The drain is the silicon substrate, contacted at the back of the wafer, making the HV-JFET avertical structure, as is typical for silicon power devices [4].The source-to-drain current flows between these two terminals passing through the gap in thebottom gate. As in a standard JFET, the gate voltage modulates the channel resistance. The deviceenters into saturation mode when the channel end is pinched off by the reverse bias applied betweenthe channel itself, the gates and the drain. After that point, the current drifts to the drain. In theHV-JFET, the drain is far away from the channel and the channel is shielded from the drain voltageby the bottom gate. This means the drain voltage has little influence in closing the channel or, statedotherwise, very high drain voltages must be applied to significantly affect the electrostatics at thechannel end. This has been clearly shown by TCAD numerical simulations [5] and is of paramountimportance when dealing with irradiated substrates.We fabricated the p -type JFETs in a batch of 4 wafers, each wafer differing in the implantationdose of the p -channel only. JFETs belonging to the two wafers with the lowest boron doses have thechannel pinched-off already at V gate = V . JFETs from the other two wafers are working and showdifferent pinch-off voltage. Ultimately we irradiated the JFETs with the higher pinch-off voltage asto have a larger source current in the ON state.The HV-JFETs have been entirely fabricated using a standard planar process in the siliconprocessing facility of the Instrumentation Division at BNL [6]; another effort made by CNM(Barcelona, Spain) has fabricated vertical silicon HV-JFETs using a 3D technology [7]. The– 3 – igure 3 . Measurements of the output characteristics of HV-JFETs for the different fluences, from 0 to1 . · eq / cm . Curves acquired with the same gate voltage have the same colour. planar technology used at BNL is sub-optimal: as pointed out in [6], a process involving a thinepitaxial layer deposition after the bottom gate implantation avoids some undesired effects ("horn"effect), where the tails of the deep bottom gate compensate for the channel implant at the gapedges. However, this fabrication must be seen as a proof of concept of the device and improvedperformance can be expected in an optimized fabrication. Several p -type HV-JFETs were irradiated at the TRIGA nuclear reactor of JSI, Ljubljana, Slovenia.The chosen irradiation fluences were 4 · , 8 · and 1 . · eq / cm . Typical curves forthe three irradiation levels as compared to the pre-irradiation case are shown in Figure 3. To measurethe output characteristics, the drain voltage is swept from 0 V to the breakdown voltage (whichhappens between gate and drain) and the currents at the source and the gate are measured. Thedrain voltage is applied through the chuck of a probe station and supplied by a Keithley 2410, whilethe gate and the source are contacted by needles mounted on the probe station micro-manipulators;the current is then read-out by an HP4145B. However, to limit the power dissipation within theJFET, we had to limit the drain voltage for the highest currents (i.e. at the lowest gate voltages).In particular, due to the unfortunate absence of smaller devices, current-voltage characteristics forzero gate voltage are not measurable at high voltage where the device is in saturation.– 4 – igure 4 . Measurements of the gate current for typical HV-JFETs irradiated at different fluences. Solidlines are for V gate = gate = The breakdown voltage is independent from the irradiation level: it happens for V drain =
300 V,before and after irradiation. TCAD studies [5] show that the region with the highest electricfield, where the breakdown likely originates, is at mid gap at the channel-top gate junction. Thetermination region, made by 16 floating guard rings surrounding the bottom gate has been measuredto be able to sustain voltages in excess of 600 V, pre-irradiation. Irradiation is expected to increasethe voltage handling capability of such termination, however, a direct measurement is not possiblesince the active region of the JFET breaks down much earlier.For the same gate voltage, the source-to-drain current in saturation decreases with irradiation.Stated differently, the irradiation shifts the pinch-off voltage at lower gate voltages. This is due tothe radiation-induced acceptor removal [3] in the channel, that increases the resistance of the sameand therefore decreases the current.Of particular interest is the shift of the drain saturation voltage by increasing the irradiationfluence. As in a standard JFET, as well as in the linear region of a HV-JFET (where the channel endis not yet pinched-off by the combined action of the gates and the drain), the I-V curves lay togetheron the same envelope, for any gate voltage. This is evident for the highest irradiation fluence, whileit holds with good approximation for the lowest. The shape of this envelope is a strong functionof the irradiation fluence, featuring a lower concavity at the higher fluences. As in the standardJFET, the drain supplies at the end of the channel the voltage that, summed up with the gate voltage,closes the channel. At the fluences used in this work, the channel, which is relatively highly doped,experiences an acceptor removal [3] and one expects that lower drain voltages are needed to closethe channel. This clearly does not happen: higher drain voltages need to be applied as the irradiationlevel increases. This points to the fact that other phenomena are at play: the physical interpretationthat we propose to explain this behaviour is the subject of section 4.Figure 4 reports the gate leakage currents for three HV-JFETs irradiated at different fluences.For clarity sake, only gate currents for V gate = gate = leakage = V · α · φ , where V is the volume (1 mm x 1 mm x 50 µ m), α is thedamage constant (having a value of α = · − A / cm) and φ is the fluence (n eq / cm ). As canbe seen in Figure 4, gate currents hardly saturate at the depletion voltage, making the extraction ofthe damage constant not realistic. However, taking for I leakage the gate current at full depletion, amaximum value for the damage constant slightly larger than a factor of two than the one reportedin the literature can be extracted.If such a JFET had to be used as a switch after a fluence of 1 . · eq / cm , a leakagecurrent of a few mA (which is the room temperature leakage current of one cm large siliconsensor 200-300 µ m thick) would flow from source to drain only for V drain >
200 V in the ON state,resulting in a very high power dissipation of about 1 W within the device. Higher voltages must beapplied by the voltage supply too, making all the system too impractical to be used. To enter theOFF state, the JFET can be closed by a low gate voltage (2V) and the current it draws is acceptable(consisting of the leakage current generated within the depleted - but irradiated - substrate, orderof 10 µ A). However, for this particular JFET, the breakdown voltage does not satisfy the HV-Muxrequirements.
Table 1 . Trap parameters. trap type energy level (eV) density (cm − ) σ n (cm − ) σ p (cm − )acceptor E c − .
42 1 . · φ · − · − acceptor E c − .
46 0 . · φ · − · − donor E v + .
36 0 . · φ . · − . · − Figure 5 shows TCAD simulations of a HV-JFET having the geometry of Figure 2. The SILVACOsimulator has been used [8]. Standard models (without any impact ionization model activated) havebeen used. Simulations of the radiation damage are obtained using three traps as described by the"Perugia" model [9], as shown in Table 1. In the table, the "energy level" is the energy gap in eVfrom the conduction or the valence band for an acceptor or donor trap, respectively; "density" is thedensity of a trap in cm − , φ is the fluence, σ n ( p ) is the capture cross section for electrons (holes).The Perugia model does not simulate the acceptor removal.By changing the density of the traps according to the fluence, the I-Vs of Figure 5 are obtained.As experienced in the measurements of real devices, TCAD simulations also predict increasingdrain voltages at the onset of saturation by increasing the fluence. This is due to the build-up ofpositive charge along the path of the hole current which is created by the ionized donor traps. Adonor trap is neutral when filled with an electron, while positively charged when empty (thus thename "donor" traps): there are no electrons to fill up such traps and the holes of the source-to-draincurrent rapidly recombine with the electrons of the filled traps. The net-positive charge createspotential barriers in the gap region that inhibit the injection of holes and block the drain voltagefrom closing the channel end. This effect is more severe at higher irradiation levels, since more– 6 –raps are generated. Acceptor traps, on the other hand, are neutral because they are not filled byelectrons, and being neutral do not alter the electrostatics of the device. Therefore, larger drainvoltages must be applied to lower the potential barrier and provide the voltage sufficient for thepinch-off of the channel end.Substrate effects of increased substrate resistance which quenches the current by providing aresistive drop are excluded, since the resistivity saturates at these irradiation fluences [10] [11].To visualize these effects, the 2-dimensional map of the electrostatic potential in the gap regionfor the different irradiation fluences is plotted in Figure 6, for V gate = drain = −
100 V. Inthe not-irradiated case, the device is already in saturation: high-value (here and in the followingthe absolute value is understood) equipotential lines enter the gap region, reach the channel endand pinch it off. This is not the case for irradiated devices, where potentials closer to zero arepresent. The low voltage present in the case of a fluence of 4 · cm − is barely effective inclosing the channel, while at the higher irradiation levels this voltage is not large enough to closethe channel: lower potentials exist in the gap region with the consequence that higher drain voltagesmust be applied to have values high enough to close the channel. Moreover, a potential barrierexists between the channel and the substrate across the gap region, that the holes have to cross topass from channel to drain. This potential barrier is lowered by the application of higher drainvoltages.Let’s also consider the horizontal cutline along the lowest potential of Figure 6 and shown inFigure 7: the higher the irradiation level the lower the potential value in the gap region, while highvoltages are needed in this region to close the channel. Also, a lower (closer to zero) potentialmeans a higher value of the potential barrier for the holes to cross before going to the substrate.This is correlated with the the positive charge created by the ionized donor trap density (also plottedin Figure 7).Finally, from Figure 5 it can be noted that, for a same gate voltage, the drain current insaturation is independent from the fluence, dramatically differing from measurements. This, assaid above, is due to the fact that the Perugia model does not account for any acceptor removalphenomena. HV vertical silicon JFETs, developed and fabricated at BNL, have been irradiated up to a fluenceof φ = . · n eq cm − , which is the maximum fluence that the switch for the HV-Mux of theATLAS ITk at the HL-LHC is expected to be exposed to. A static characterization at the probestation has been performed to assess their radiation hardness. The chosen JFET, which belongedto the very first fabrication and must be seen as prototypes, featured a breakdown voltage belowthe required by the HV-Mux specs; however it is found to be unaffected by the irradiation level.Most notably, by measuring the output characteristics (i.e. drain currents vs drain voltage fordifferent gate voltages), we can see how the drain saturation voltage is strongly dependent on thefluence: at low drain voltages the drain currents stay on a common envelope, as in a standard JFET,while they depart from it at increasingly higher voltages as the fluence is increased. NumericalTCAD simulations explain the phenomenon to be due to a positive charge build-up, caused by theempty ionized donor traps induced by the irradiation. Consequently, a potential barrier is created– 7 – igure 5 . Simulated output characteristics for different fluences using the geometry of Figure 2. Figure 6 . Simulated electrostatic potential in the region of the gap, for different irradiation fluences. Drainvoltage = - 100 V. The white colour maps equipotential regions at +0.5 V; black at -1 V. Potential, ionizeddonor trap density and charge density along the shown cutline are plotted in Figure 7. The cutline has beendrawn in the region where the potential has a maximum. – 8 – igure 7 . Top, cutlines of the electrostatic potential along the line shown in Figure 6, for different values ofthe fluence Φ , in n eq / cm . The tip of the bottom gate is at x = µ m. Middle, density of the ionized donortraps along the same cutline, log scale. Bottom, charge density. Drain voltage = - 100 V. – 9 –or the holes (of the source-to-drain current) to cross. To be used as a switch in the HV-Mux,in the ON state the current has to be in the order of a few mA which requires for this family ofJFETs an operational voltage of V drain >
200 V, causing a large power dissipation within the device.Breakdown voltage, ON and OFF currents are strongly inter-correlated and depend on many factors(size, channel doping concentration, geometry) as well as on the process flow: an optimization andan improvement of these prototype JFETs that push their performance towards in-spec HV-Muxswitch is certainly possible. However, a not negligible power dissipation within the device is alwaysexpected, particularly after irradiation; due to the outstanding performance of GaN JFETs, siliconHV JFETs are not going to be further considered for this application.
Acknowledgments
The team at the TRIGA nuclear reactor at JSI (Ljubljana, Slovenia) is deeply acknowledged for hav-ing performed the irradiation. This material is based upon work supported by the U.S. Departmentof Energy under grant DE-SC0012704. This research used resources of the Center for FunctionalNanomaterials, which is a U.S. DOE Office of Science Facility, at Brookhaven National Laboratoryunder Contract No. DE-SC0012704.
References [1]
Technical Design Report for the ATLAS Inner Tracker Strip Detector ,https://cds.cern.ch/record/2257755/?ln=en .[2] E. G. Villani, P. Phillips, J. Matheson, Z. Zhang, D. Lynn, P. Kuczewski, L. Hommels, I. Gregor,M. Bessner, K. Tackmann, F. Newcomer, E. Spencer, and A. Greenall,
HVMUX, a high voltagemultiplexing for the ATLAS Tracker upgrade , Journal of Instrumentation, C01076 .[3] M. Moll,
Acceptor removal - Displacement damage effects involving the shallow acceptor doping ofp-type silicon devices , PoS(Vertex2019)027 .[4] S. Ghandhi,
Semiconductor Power Devices , Wiley (1987) .[5] G. Giacomini, W. Chen, and D. Lynn,
A HV silicon vertical JFET: TCAD simulations , NuclearInstruments and Methods in Physics Research A (2019) 119–124.[6] G. Giacomini, W. Chen, and D. Lynn,
Fabrication and Measurements of High-Voltage Silicon JFETs ,Journal of Instrumentation, C01076 .[7] P. Fernández-Martínez, D. Flores, S. Hidalgo, D. Quirion, R. Durà, and M. Ullánl,
First fabrication ofa silicon vertical JFET for power distribution in high energy physics applications , NuclearInstruments and Methods in Physics Research A (2018) 269–277.[8] .[9] M. Petasecca, F. Moscatelli, D. Passeri, and G. U. Pignatel,
Numerical Simulation of RadiationDamage Effects in p-Type and n-Type FZ Silicon Detectors , IEEE Transaction on Nuclear Science (2006) 2971.[10] G. Lutz, Effects of deep level defects in semiconductor detectors , Nuclear Instruments and Methods inPhysics Research A (1996) 234–243. – 10 –
11] Z. Li,
Modeling and simulation of neutron induced changes and temperature annealing of N ef f andchanges in resistivity in high resistivity silicon detectors , Nuclear Instruments and Methods in PhysicsResearch A (1994) 105–118.(1994) 105–118.