Fabrication of quantum dots in undoped Si/Si 0.8 Ge 0.2 heterostructures using a single metal-gate layer
T. M. Lu, J. K. Gamble, R. P. Muller, E. Nielsen, D. Bethke, G. A. Ten Eyck, T. Pluym, J. R. Wendt, J. Dominguez, M. P. Lilly, M. S. Carroll, M. C. Wanke
FFabrication of quantum dots in undoped Si/Si . Ge . heterostructures using a singlemetal-gate layer T. M. Lu, a) J. K. Gamble, R. P. Muller, E. Nielsen, D. Bethke, G. A. Ten Eyck, T.Pluym, J. R. Wendt, J. Dominguez, M. P. Lilly, M. S. Carroll, and M. C. Wanke Sandia National Laboratories, Albuquerque, New Mexico 87185,USA (Dated: 5 November 2018)
Enhancement-mode Si/SiGe electron quantum dots have been pursued extensivelyby many groups for their potential in quantum computing. Most of the reporteddot designs utilize multiple metal-gate layers and use Si/SiGe heterostructures withGe concentration close to 30%. Here we report the fabrication and low-temperaturecharacterization of quantum dots in Si/Si . Ge . heterostructures using only onemetal-gate layer. We find that the threshold voltage of a channel narrower than1 µ m increases as the width decreases. The higher threshold can be attributed tothe combination of quantum confinement and disorder. We also find that the lowerGe ratio used here leads to a narrower operational gate bias range. The higherthreshold combined with the limited gate bias range constrains the device design oflithographic quantum dots. We incorporate such considerations in our device designand demonstrate a quantum dot that can be tuned from a single dot to a double dot.The device uses only a single metal-gate layer, greatly simplifying device design andfabrication. a) Electronic mail: [email protected] a r X i v : . [ c ond - m a t . m e s - h a ll ] A ug lectron spins are one of the most promising candidates for implementing solid-statequbits . Si, in particular, is a widely pursued host material for spin qubits, due to itslong coherence times resulting from its weak spin-orbit interaction and the possibility ofobtaining isotopically pure Si which has zero nuclear spin . In Si, manipulation of indi-vidual electron spins can be achieved in electrostatically defined quantum dots in additionto donor-bound electrons as proposed by Kane . A typical starting platform for makingquantum dots is a two-dimensional electron gas (2DEG), which either resides at the Si/SiO interface in the case of Si metal-oxide-semiconductor field-effect transistors (MOSFETs),or in a strained Si quantum well in the case of Si/SiGe heterostructures. A Si/SiGe het-erostructure has epitaxial interfaces, which are much less disordered than amorphous SiO on Si and result in much higher electron mobilities. For Si/SiGe heterostructures, one caneither use modulation-doping and fabricate gates to locally deplete electrons, or employa MOSFET-like enhancement-mode architecture and induce electrons only where desired.Due to higher starting mobility and better device stability, the enhancement-mode archi-tecture has gained popularity in recent years. Device designs, dot operation, and qubitmanipulation have all been reported using this enhancement-mode architecture .In most of the reported dot designs, the starting Si/SiGe heterostructure has a Ge con-centration close to 30%, and the gates used to define quantum dots are structured in multiplemetal layers. There has not been much discussion on the choice of this combination. Sinceelectron mobility is the most obvious and convenient gauge for material quality and therecord electron mobility was demonstrated in a heterostructure with a Ge content of 20%,we chose the same composition for the relaxed SiGe buffer layers as we started fabricatingSi/SiGe quantum dots. The higher achievable mobility was expected to reduce the impactof disorder. At first glance, the main difference between Si/Si . Ge . and Si/Si . Ge . issimply the barrier height in the 2DEG normal direction. This difference in barrier height isnaively not expected to mandate a change in quantum dot design, since most design con-siderations center around creating lateral confinement of electrons to form quantum dots.Surprisingly, we learned that a reduced Ge concentration affects device performance indi-rectly but strongly. In this work we study the physical mechanisms of this effect throughlow-temperature experiments and simulations, and discuss the constraints imposed on devicedesign. Accounting for the constraints, we demonstrate electrical control of quantum dots ina Si/Si . Ge . heterostructure. Furthermore, the fabrication process flow presented here uses2nly a single metal-gate layer, which greatly simplifies device fabrication, shortens deviceturnaround times, and improves yield by avoiding potentially leaky metal-insulator-metalstacks.In this work we used undoped Si/Si . Ge . heterostructures grown by Lawrence Semi-conductor Research Laboratory. A virtual substrate was made by growing a 2- µ m linearlygraded buffer layer on a Si wafer at a grading rate of 10%/ µ m, followed by a 1- µ m Si . Ge . relaxed buffer layer. Chemical mechanical polishing (CMP) removed 150 nm of the relaxedbuffer layer to reduce surface roughness. After CMP, epi-layers of 400 nm Si . Ge . , 20nm Si, 35 nm Si . Ge . , and 3 nm Si were grown in order. The heterostructures were pro-cessed in the Si foundry at Sandia National Laboratories. A similar process flow for SiGeheterostructures has been reported earlier . Electron-beam lithography (EBL) defined thenanostructured gate patterns. 15 nm Al O and 100 nm Al were then deposited in the samerun, followed by lift-off. The Al O layer that insulates the gate from the substrate wasformed by depositing Al in the presence of O .We made a series of narrow transistors with variable channel widths, ranging from 100nm to 5 µ m wide. Each narrow gate was 2 µ m long. At each end of a narrow gated region,the enhancement gate was flared quickly to a width exceeding 10 µ m and was extended tooverlap two high doped regions on each end of the narrow wire to make two ohmic contactson each end. The device threshold voltages were characterized at 4 K by monitoring theonset of channel current at a quasi-dc drain-source bias ( V DS ) of 1 mV against the gatevoltage ( V G ). Using the four ohmic contacts for each device, we extracted two thresholdvoltages, one for the narrow channel, and one for the wide channel. The difference in thetwo threshold voltages for each device was then tabulated. Some narrow channels did notturn on below V G = 2 V, the highest voltage applied. These devices were excluded fromthe calculation of threshold shifts. Fig. 1 (c) shows the average shift and the standarddeviation of threshold voltages of the narrow channels, and Fig. 1 (d) shows the fractionof working devices. The non-uniform standard deviation arises from outliers that had athreshold voltage much higher than the other devices in the same group.It is clear from Fig. 1 (c) and (d) that the threshold voltage of a narrow channel shiftshigher and a larger fraction of devices do not turn on as the channel gets narrower. In thecase of 100-nm-wide channels, none of the devices showed turn-on below V G = 2 V. This isin stark contrast to 100-nm channel widths routinely achieved using similar structures with3 30% Ge concentration . We attribute the non-working channels and the threshold shiftsto the lower Ge concentration used in this work in combination with two other mechanisms,lateral quantum confinement and disorder.To understand the lateral quantum confinement effect, we performed simulations to an-alyze the nanowire geometry explored by the experiment. For each wire width, we com-puted the electrostatic landscape by solving Poisson’s equation in 2D with the finite elementmethod in COMSOL Multiphysics using the geometry shown in Fig. 1 (a). We then usedthis potential energy landscape as input to Schr¨odinger’s equation, and solved for the ener-gies of the 1D nanowire sub-bands. Since different wire widths produce different 2D groundstate energies for the same applied voltage, the lowest sub-band begins filling at differentapplied voltages for different wire widths.To check if this model is consistent with our experiment, we note that the ground stateenergy of the 2D system is linear with gate voltage, as shown by the computational resultsin Fig. 1 (b). Hence, we may write E L = m L V G , (1)where E L is the ground state energy of the wire of width L , m L is the slope (determinedcomputationally), and V G is the applied gate voltage. By inverting this relationship, we canexpress the voltage shift of a narrow wire compared to an infinitely wide wire as,∆ V L = E m L m ∞ ( m ∞ − m L ) , (2)where m ∞ is the slope in the infinite wire-width limit, and E represents a constant thresholdenergy independent of wire width. We assume the threshold occurs when the ground stateenergy level of a specific wire, E L , reaches E . Noting that the values of m L saturate forthe wide wires we considered, we take m ∞ ≈ m = −
930 meV/V. Treating E as a freeparameter and fitting the model to the data using a chi-squared test statistic, we obtaineda goodness of fit p = 0 . Unfortunately for Si/SiGe heterostructure FETs, there existsan upper density limit . For shallow Si quantum well channels this maximum densitysignals the onset of population of a surface channel at the oxide/semiconductor interface.For deep Si quantum wells, a non-equilibrium distribution of electrons collect in the well,with a maximum density controlled by tunneling to a parallel surface channel. A detaileddiscussion of this non-equilibrium charge distribution can be found in Ref. 12. In both cases,the saturation density is dependent on the barrier height, or in turn, the Ge concentration ofthe SiGe layers, with the maximum density independent of the channel depth in the lattercase . The wells used here are considered deep wells and as such, the electron density canbe higher than the thermal equilibrium value and is dynamically limited by slow tunneling.Experimentally this upper density limit is ∼ × cm − for Si . Ge . barriers and ∼ × cm − for Si . Ge . barriers . We obtained a similar upper density limit in our structuresusing Hall bar testers fabricated from the same material. This density limit, nonlinearin barrier height, limits the tunable density range in Si/Si . Ge . to less than half thedensity range in Si/Si . Ge . . The maximum density results in a maximum Fermi energy.For gate voltages beyond the density saturation bias, a possibly more serious effect occurs,namely, the oxide/semiconductor interface forms a second accumulation layer and eventuallyaccumulates a high enough electron density to become conducting . When the surfacechannel conduction occurs, this surface channel screens the electric fields to the buried Siquantum well channels, and reduces the electron density in the Si quantum well to its thermalequilibrium value. The thermal equilibrium value could be below the conduction threshold,such that the channel conductivity drops to zero. This appears to happen in all our samples,in which we observe a sudden drop in current to zero at a gate bias beyond threshold, asshown in the inset of Fig. 1 (d).Since the current in our devices has to flow serially through both the wide and narrow5hannel areas, the maximal Fermi energy and the sudden turnoff pose a serious problemif the maximum Fermi energy in the wide gated channel area is not much higher or evenlower than the conduction threshold energy of the narrow channel. In the former case, thenarrow channel barely turns on before the wide channel turns off, and hence the resistanceis very high. In the latter case, when the lateral confinement lifts the threshold energy levelsignificantly, the narrow wire will not reach threshold until the gate is biased beyond theturn-off voltage of the wide channel area. Thus for the narrowest wires there will never bea simultaneous conduction path through both regions. Using Si/Si . Ge . heterostructuresinstead of Si/Si . Ge . thus severely constrains the operational window of V G . A multiple-metal-layer architecture with independent controls for the reservoirs and nanostructurescircumvents this density limit problem since the potential landscape can be locally tuned.Having understood the major difference between Si/Si . Ge . and Si/Si . Ge . , we nowturn to our results of fabricating quantum dots using Si/Si . Ge . heterostructures. Sincethe main difficulty in using lower Ge concentration is the high threshold voltages for narrowchannels, the quantum dot designs have to be enlarged compared to what are used in SiMOSFETs or in Si/Si . Ge . , unless a multiple-metal-layer architecture is adopted. Forthis work we chose to use only one metal layer and therefore chose to make large quantumdots. A larger quantum dot has lower charging energies and requires lower temperatures toresolve transport features. However, the larger feature sizes are more easily fabricated. Fur-thermore, the one-metal-layer architecture has fewer fabrication steps and fewer potentiallyleaky metal-insulator-metal stacks. This simpler process flow, together with the relaxednano-patterning accuracy, significantly shortens fabrication turnaround times and improvesdevice yield.The starting wafer for the dot work had nominally identical growth parameters as pre-viously described. Here we did every step at die-level. Ti/Au alignment marks were firstdeposited, followed by ion implantation of P at 20 KeV and 75 KeV with a fluence of 5 × cm − for each energy. A rapid thermal anneal at 625 ◦ C for 30 sec activated the implanteddopants for ohmic contacts. A blanket 20-nm-thick Al O layer was deposited in an atomic-layer-deposition system at 200 ◦ C. After etching vias through Al O , we deposited a blanket2 nm Ti and 40 nm Au film. This metal layer was patterned by EBL and etched in an ionmill. The exposed metal areas were milled away, leaving nanostructure gates and bond padssimultaneously. Fig. 2 (a) shows a scanning electron micrograph of a fabricated quantum-6ot device. Also shown is the circuit setup used for the data presented below. The namesof the gates are labeled in yellow. The narrowest point of the channel had a width of ∼ He cryostat with a base temperature of ∼ V DS = 10 µ V using standard lock-in techniques. We focused on the upper channeland varied the voltages for UL, UC, and UR to form quantum dots. The voltages used forAGU, AGL, LL, LC, and LR were kept constant at 0.633, -0.35, 0, 0, and 0 V, respectively,for the data presented here. In Fig. 2 (b) we show a series of stability plots against theUL and UR gates at different UC voltages. At low (less negative) UC, single-quantum-dotbehavior is dominant in the lower left corner of a UR vs. UL plot, with approximately equalcouplings to the UL and UR gates. Upon making UC more negative, the dot is broken upinto two halves by the electrostatic potential, and forms a pair of quantum dots coupledby tunneling. The isolated transport peaks observed showed the expected triple points fortunnel-coupled double-quantum-dots . From stability diagrams, we extract the followinggate-dot capacitances for the double-dot system: C UL,L = 4.0 aF, C UC,L = 5.2 aF, C UR,L =1.2 aF, C AGU,L = 63 aF, C AGL,L = 13 aF, C LL,L = 1.3 aF, C LC,L = 1.4 aF, C LR,L = 0.48aF, C UL,R = 1.3 aF, C UC,R = 5.2 aF, C UR,R = 4.0 aF, C AGU,R = 79 aF, C AGL,R = 13 aF, C LL,R = 0.63 aF, C LC,R = 1.3 aF, C LR,R = 0.48 aF. These capacitances are consistent with alithographic double-dot defined by the gates. The inter-dot tunnel barrier is not only tunedby the UC gate, but also by the UL and UR gates, as is evidenced from the transition fromsingle-dot-like to double-dot-like characteristics moving from the upper right corner to thelower left corner at a fixed UC voltage. This is a trade-off of using a single-metal-gate-layerdesign; controls over tunnel barriers and dot occupations are more intertwined together andrequire more sophisticated device tuning.To corroborate our single to double-dot interpretation of Fig. 2 (b), we performed capac-itive modeling of our nanostructure using FastCap to obtain a simulated charge stabilitydiagram. We used voltages identical to our experiment, modeled the electrical leads belowAGU as a metallic brick, and the two quantum dots as 10 nm thick conductive bricks with400 ×
400 nm in-plane dimensions, as shown in Fig. 2 (a). The two dots were separated bya distance d , which we varied. As shown in Fig. 2 (c), by changing the distance from 0 . . Ge . heterostructures, and were able to induce a single-dot to double-dottransition. The presented fabrication process flow requires only one metal-gate-layer for allgates and bond pads, significantly reducing device fabrication turnaround times. This mayfind use in situations where high throughput of simple quantum dots is required, such asstudying the statistics of quantum dot properties.This work was performed, in part, at the Center for Integrated Nanotechnologies, aU.S. DOE, Office of Basic Energy Sciences, user facility. Sandia National Laboratories is amulti program laboratory managed and operated by Sandia Corporation, a wholly ownedsubsidiary of Lockheed Martin Corporation, for the U.S. DOE’s National Nuclear SecurityAdministration under contract DE-AC04-94AL85000. REFERENCES D. Loss and D. P. DiVincenzo, Phys. Rev. A , 120 (1998). A. M. Tyryshkin, S. A. Lyon, A. V. Astashkin, and A. M. Raitsimring, Phys. Rev. B ,193207 (2003). F. A. Zwanenburg, A. S. Dzurak, A. Morello, M. Y. Simmons, L. C. L. Hollenberg,G. Klimeck, S. Rogge, S. N. Coppersmith, and M. A. Eriksson, Rev. Mod. Phys. ,961 (2013). B. E. Kane, Nature , 133 (1998). F. Schffler, Semicond. Sci. Tech. , 1515 (1997). T. M. Lu, J. Liu, J. Kim, K. Lai, D. C. Tsui, and Y. H. Xie, Applied Physics Letters ,182114 (2007). T. M. Lu, N. C. Bishop, T. Pluym, J. Means, P. G. Kotula, J. Cederberg, L. A. Tracy,J. Dominguez, M. P. Lilly, and M. S. Carroll, Appl. Phys. Lett. , 043101 (2011). D. Kim, Z. Shi, C. Simmons, D. Ward, J. Prance, T. S. Koh, J. K. Gamble, D. Savage,8. Lagally, M. Friesen, S. N. Coppersmith, and M. A. Eriksson, Nature , 70 (2014). K. Eng, T. D. Ladd, A. Smith, M. G. Borselli, A. A. Kiselev, B. H. Fong, K. S. Holabird,T. M. Hazard, B. Huang, P. W. Deelman, I. Milosavljevic, A. E. Schmitz, R. S. Ross,M. F. Gyure, and A. T. Hunter, Science Advances , e1500214 (2015). D. M. Zajac, T. M. Hazard, X. Mi, K. Wang, and J. R. Petta, Appl. Phys. Lett. ,223507 (2015). T. M. Lu, D. C. Tsui, C.-H. Lee, and C. W. Liu, Appl. Phys. Lett. , 182102 (2009). T. M. Lu, C.-H. Lee, S.-H. Huang, D. C. Tsui, and C. W. Liu, Appl. Phys. Lett. ,153510 (2011). C.-T. Huang, J.-Y. Li, K. S. Chou, and J. C. Sturm, Appl. Phys. Lett. , 243510 (2014). W. G. van der Wiel, S. De Franceschi, J. M. Elzerman, T. Fujisawa, S. Tarucha, and L. P.Kouwenhoven, Rev. Mod. Phys. , 1 (2002).9 a)(b)
20 nm35 nm15 nm100 nm V G Si Ge Si Ge SiAl O E ( m e V ) − − − − −
200 V G (V)0 0.5 1.0 Y i e l d ( w ) μ m)0.1 1 5 (c)(d) T h r e s ho l d v o l t age s h i ft ( V ) − V o l t age fl u c t ua t i on ( V ) μ m)0.1 1 5 V o l t age fl u c t ua t i on ( V ) FIG. 1. (a): Schematic cross-section and top view of the measured/modeled FET. The arrowsillustrate the current paths of the wide and narrow channels. (b): Calculated ground state energyof the channel produced by applying a voltage on the gate indicated in (a). The lines correspondto the wire widths measured in panel (c). (c): Threshold voltage shift (solid dots) and its standarddeviation (x markers) as a function of wire width. The line is the model fitted to a single-parametermodel, obtaining a goodness of fit p = 0 . V DS = 1 mV for a 200-nm widechannel (right curve) and an 800-nm wide channel (left curve). Bottom inset: a representativeturn-on curve showing that the channel shuts off beyond a critical gate voltage. IG. 2. (a) Scanning electron micrograph of the device. Lighter gray with yellow labels are Ti/Augates on top of the Si/SiGe substrate. The cyan pseudo-colored regions are exposed Al O . Thecapacitance calculations assume two square quantum dots with side length 400 nm as indicated ingreen. These two dots are separated by a distance d . (b) Stability diagrams for the quantum dotin the upper channel at V UC = -0.85, -0.875, -0.9, -0.925, -0.95, and -0.975 V. The measurementtemperature was 0.3 K, and the drain-source bias was 10 µ V. (c) Capacitance simulations fordiffering dot separation d . We see that even a modest dot separation of 10 nm is sufficient totransition from single- to double-dot behavior. These calculations indicate that the observed chargestability diagrams in (b) likely describe a transition between lithographic dots.. We see that even a modest dot separation of 10 nm is sufficient totransition from single- to double-dot behavior. These calculations indicate that the observed chargestability diagrams in (b) likely describe a transition between lithographic dots.