LTARS: Analog Readout Front-end ASIC for Versatile TPC-applications
Tetsuichi Kishishita, S. Sumomozawa, T. Kosaka, T. Igarashi, K. Sakashita, M. Shoji, M. M. Tanaka, T. Hasegawa, K. Negishi, S. Narita, T. Nakamura, K. Miuchi
aa r X i v : . [ phy s i c s . i n s - d e t ] A ug Prepared for submission to JINST
LTARS: Analog Readout Front-end ASIC for VersatileTPC-applications
T. Kishishita, a , , S. Sumomozawa, b T. Kosaka, b T. Igarashi, b K. Sakashita, a M. Shoji, a M. M.Tanaka, a T. Hasegawa, a K. Negishi, b S. Narita, b T. Nakamura c , and K. Miuchi c a KEK, High Energy Accelerator Research Organization1-1 Oho, Tsukuba, 3050801, Ibaraki, Japan b Iwate University,4-3-5 Ueda, Morioka, 0208551, Iwate, Japan c Kobe University,1-1 Nada-ku, Rokkodaicho, Kobe, 6570013, Hyogo, Japan
E-mail: [email protected]
Abstract: W e designed a versatile analog front-end chip, called LTARS, for TPC-applications,primarily targeted at dual-phase liquid Ar-TPCs for neutrino experiments and negative-ion µ -TPCs for directional dark matter searches. Low-noise performance and wide dynamic range aretwo requirements for reading out the signals induced on the TPC readout channels. One ofthe development objectives is to establish the analog processing circuits under low temperatureoperation, which are designed on function block basis as reusable IPs (Intellectual Properties). Thenewly developed ASIC was implemented in the Silterra 180 nm CMOS technology and has 16readout channels. We carried out the performance test at room temperature and the results showedan equivalent noise charge of 2695 ±
71 e − (rms) with a detector capacitance of 300 pF. The dynamicrange was measured to be 20–100 fC in the low-gain mode and 200–1600 fC in the high-gainmode within 10% integral nonlinearity at room temperature. We also tested the performance atthe liquid-Ar temperature and found a deterioration of the noise level with a longer shaper time.Based on these results, we also discuss a unique simulation methodology for future cold-electronicsdevelopment. This method can be applicable to design the electronics used at low temperature. Keywords:
Time projection chambers, Front-end electronics for detector readout, Liquid detectors Corresponding author. Also at SOKENDAI, The Graduate University for Advanced Studies. ontents
In recent studies in particle and astro-particle physics, detectors with high-resolution positionalimaging are often desired to explore new physics phenomena because the topological informationcan be utilized to discriminate the signature of the new physics phenomena from backgroundevents. These detectors require huge numbers of readout channels and advanced electronics playan important role in handling such large numbers of readout channels. To meet this need, we aredeveloping front-end electronics for versatile applications of time projection chambers (TPCs) for ajoint project called
LTARS (Low Temperature Analog Readout System), located at KEK, Kobe, andIwate Universities. We plan to use this readout system for the directional dark matter experiments[1, 2] and for the next-generation neutrino oscillation experiments [3].TPC-based three-dimensional (3D) tracking detectors are thought to be one of the best detectorsfor the directional direct dark matter search experiments and several groups have developed prototypedetectors [4, 5].
NEWAGE is one of these directional dark matter search experiments and has beenleading in directional sensitivity [1]. One of the next steps needed to improve the sensitivity isto utilize a negative-ion drift gas, which enables full-volume fiducialization through 3D positionreconstruction of the event vertex [6, 7]. These TPCs are called negative-ion (NI) µ -TPCs andthe detector concept is shown in the left of Figure 1. In the NI µ -TPCs, the ionized electrons arecaptured by the gas molecule immediately after ionization thereby generating negative ions. These– 1 –ons are drifted instead of the electrons in the NI µ -TPCs. Some types of negative ion gases couldcontain more than one species of negative ion ( SF and SF in Figure 1). Each of these ions aredrifted with different velocities. The arrival time difference provides information on drift length,or, the absolute position on the electric field direction. This new concept helps to improve thesensitivity by rejecting background events from the readout plane (indicated as MPGDs in Figure1) and the cathode plane; this was not possible with the self-triggering TPCs.A large scale O (10 kt) liquid argon time projection chamber (LAr-TPC) will be utilized as a 3D-tracking device for studies of next-generation neutrino oscillation, nucleon decay, and astrophysicalneutrinos. Toward the realization of such a large-scale detector, a world-wide R&D effort on kilo-ton-scale LAr-TPC demonstrators is underway [8]. One approach to read out the ionized electronsignals is to use a dual-phase LAr-TPC [9]. The detector concept is shown in the right of Figure 1.In the dual-phase TPC, the ionized electrons are extracted from the liquid phase (indicated as LArin Figure 1) to the gas phase (GAr), and the extracted electrons are multiplied with a thick-GEM(Gas Electron Multiplier) and collected with a two-dimensional strip anode. The main advantageof the dual-phase readout is the high signal-to-noise ratio afforded by the gas multiplication. Thisenables a longer drift length because the signal is amplified even though some primary electronsare lost by impurities in the LAr. The high signal-to-noise ratio also benefits the physics sensitivityfor the neutrino oscillation, nucleon decay, and astrophysical neutrino signals. MPGDs to DAQCathode electricfield- (cid:1) signal readoutelectronics (cid:1)(cid:1) -- SF - SF - SF gas SF -recoil nuclei q tSF - Cathode + - + + + + electricfield --- - anode to DAQ thick-GEM signal readoutelectronicsionizationelectrons Figure 1 . Detector concepts of the NI µ -TPC (Left) and the dual-phase LAr-TPCs (Right). The signal timescale is much longer than that of electrons in typical gas TPCs, i.e. , ≈ − cm/ µ sfor the NI µ -TPCs and ≈ − cm/ µ s for the LArTPCs, respectively. Therefore, the electronics hasa lot of similarities, but is different from the standard electronics for the TPC. Additionally, a widedynamic range together with a high signal-to-noise ratio is required for the readout electronics. Inthe case of the NI µ -TPCs, typical signals are 3 fC for the minority species (indicated as SF inFigure 1) and 80 fC for the main species ( SF ) [11, 12]. On the other hand, the typical ionizationsignal in the LArTPCs is ≈ fC, assuming one order of magnitude of the thick-GEM gains, for aminimum ionization particle (MIP). The signal on one readout channel for events associated withelectromagnetic or hadronic showers is about 50 times larger than 1 MIP signals. The detectorcapacitances seen from the ASIC input are both estimated as ∼ pF. A fine spatial resolution is– 2 –lso necessary for both detectors, and it results in a huge number of readout channels as a wholedetector system. We also need to take the operating temperatures into consideration.Whereas the readout electronics can be operated at room temperature (RT) in the NI µ -TPC,the front-end needs to be operated at ≈ -185 ◦ C for in the LArTPCs. This thermal constraint comesfrom a practical issue that the analog front-end electronics must be located as close as possible tothe strip readout in order to minimize the detector capacitance.To satisfy various requirements from both experiments, we have developed a series of readoutASICs in a 180 nm CMOS technology. The circuits are designed on a function-block basis asreusable components. In this paper, we report on the performance of a newly developed 16-channelASIC at RT and the functionality under the LAr temperature (LT) operation. We optimized thetransistor parameters of the previous prototype chip, taking special care in the layout to improvelow-noise characteristics [10]. One of the objectives of LTARS development was to generate cold-electronics ’know-how’ and to clarify issues for future system-integration, e.g. , operating methodsof the ASICs at LT, and geometrical constrains on readout systems for a huge number of channels.We describe the ASIC design in Section 2, report on its performance at RT and LT in Sections 3 and4, respectively, discuss our simulation methodology for cold-electronics and future developmentsin Section 5, and conclude in Section 6.
The physical layout of the readout ASIC implemented in the Silterra 180 nm CMOS technologyis shown in Figure 2. Technological parameters and requirements for the ASIC are listed inTable 1. The chip includes 16 identical signal processing channels. The block diagram of eachchannel is shown in Figure 3. The TPC readout channel is connected to an input (AIN) of thecharge-sensitive amplifier (CSA) by an off-chip capacitor, while test pulses can be injected via anon-chip AC-coupling capacitor C tp = pF. The CSA is based on a folded-cascode configurationwith a p-channel input transistor and a regulated-cascode configuration is implemented to improvethe open-loop gain for large detector capacitances. A transfer-gate type FET is employed for theCSA DC-feedback component. Two distinct feedback capacitors are implemented for dynamicgain-switching by using a metal-insulator-metal structure. The feedback capacitor is initially set at C f , HG = fF. This state corresponds to a high-gain (HG) mode and it copes with a narrow rangesignal of < fC. The CSA output is fed into a discriminator to select the gain mode. Once theamplitude of the CSA exceeds a certain threshold, which is given by a 6-bit DAC, a discriminatorfollowed by an RS-type flip-flop latches the switch on the additional feedback capacitance. Thisstate functions as a low-gain mode (LG) with a capacitance value of C f , LG = . pF. As a result,the overall voltage gain is more than 10 times smaller than that in the HG mode. After reading outthe analog output (AOUT) and the gain information (COMP_FBIN), the reset signal (RST) suppliedexternally releases the latched signal and the overall circuit returns to the idle state. The influenceof the switching noise on the noise performance is negligible compared to the large input signalsrequired to switch on the LG mode. The dynamic-switching behaviors have been demonstrated inthe prototype chip, and this unique property makes the chip multi-purpose, not only for LAr-TPCsbut also NI µ TPCs [10]. – 3 – CR-RC band-pass filter is composed of a pole-zero cancellation circuit (PZC) and a second-order integration low-pass filter. The capacitance and resistance values were selected to meet theequation of C f , HG · R f = C pz · R pz , and C · R = × C · R (see Fig. 3). The transfer functions inthe HG mode are described as [13] T CSA = − Q in · R f ( + sC f , HG · R f ) · ( + sC pz · R pz ) R pz , T CR − RC = − R ( sC · R + ) , T total = Q in · R f · R R pz · ( sC · R + ) , (2.1)where s denotes the complex angular frequency and Q in is the input charges. The default shaping-time of the CR-RC filter is designed as 1 µ s for the LArTPCs. This value can be switched to 4 µ sfor NI µ TPCs via a 9-bit control register. This register is equipped in each channel, while alsocontrolling the test pulse enable, monitor enable, and tuning voltage threshold. A reference currentis injected to the IBIAS node via a potentiometer inserted between the ground and supply power.The current-mirror configuration generates an internal bias current of 100 µ A that provides theproper bias current to each circuit block, e.g. , 510 µ A for the input FET in the CSA, at the currentstep of 10 µ A. Figure 2 . Physical layout of the readout ASIC. The chip size is 2.5 mm × The experimental setup and the dedicated printed circuit board (PCB) for performance testing areshow in Figure 4 left and right, respectively. The chip-mounted board (named SIRONEKO) shown– 4 – able 1 . Technological parameters and requirements to the ASIC.Technology Silterra 180 nm CMOSChip size 2.5 × The number of channels 16Supply power 1.8 V core/IO, max. 2.4 mW/chFabrication options 6 metals, deep N-well, high-value poly res., MIM cap.Detector type NI µ -TPC LAr-TPCMinimum signal charge ≈ ≈
10 fCShaping time 4 µ s 1 µ sOperating condition room temperature -185 ◦ CDetector capacitance (C det ) a ∼
300 pFDynamic range ±
80 fC for narrow range, ± − (S/N >
20) for small signals, < . × e − for large signals a Estimated from the pad size of MPGDs. C f, HG =340 fFVGG AINTP
Ctp = 2 pF
TPENB buf C pz =1.36 pF5.88 pF Comp buf
RS latch POS buf
C1 C2SlowVoffset b a nd - p ass f il t e r R1 R2
M=1 M=4VM AVSS VbnAVDD Vbp2Vbp1 Id=40 uAId=510 uA Id=1 uA charge-sensitive amp. pole-zero cancellationcircuit
AVSSAVDD 100 uA100 uA
Slow AOUTRST VthCOMP_FBIN IBIAS b i as c i r c u i t R pz R f C f, LG =6.22 pF Figure 3 . Block diagram of the processing chain. Unlabeled substrates are connected to the supply powers. on the left side of the right figure provides electrical connections between the ASIC. The semi-custom FPGA board (named GoSHIK) is also shown on the right side. A bare die was directlymounted on the PCB, and optical light was shielded during the measurements. The GoSHIK boardis an interface with a computer and provides the register control signals. This board includes8-channel ADCs (AD9637) and 8-channel voltage/current DACs (LTC2656 and MAX5550). Itprovides a flexible bias setting to the ASIC, along with an easy-to-use pattern generation from theFPGA. We chose the Xilinx XC7A100T-2FGG676C [14], and data transfer is done via an Ethernetcable with the SiTCP protocol [15]. Test pulses are generated by a function generator (AFG-21025).– 5 – igure 4 . (Left) Experimental setup at room temperature. (Right) Testboards of the ASIC.
We first injected test pulses and checked the analog output with an oscilloscope. Figure 5 showsthe waveforms in the different gain modes. The gain-switch and shaping time (1 µ s) were fixedduring the measurements. The waveforms were obtained without detector capacitance. Test pulsesare shown in blue, which correspond to input charges of -40 fC in the HG mode and -1000 fC inthe LG mode. The peaking times were measured as 1.2 µ s and 1.0 µ s, respectively. Although thepole and zero in the transfer function T CSA are not cancelled out in the LG mode (see Eq. (2.1)), theovershoot was negligible at the analog output. The difference of the peaking times is not a majorissue as long as the analog outputs are continuously sampled in parallel by ADCs, and the waveformis reconstructed in offline analysis.
HGInput = -40fC Peaking Time1.2 (cid:1) s Peaking Time1.0 (cid:0) sLGInput = -1000fC
Figure 5 . Analog outputs. The intervals on the vertical axis are 20 mV for input and 200 mV for output inthe HG mode, and 500 mV for input and output in the LG mode. The intervals on the horizontal axis are 4 µ s. All measurements were performed under the condition of C det =0 pF. The dynamic range of a typical channel is shown in Figure 6. Conversion gains were obtainedby fitting a line through the minimum and maximum points of the required dynamic range. Themeasured values were 10.0 mV/fC for positive and 10.7 mV/fC for negative polarity in the HG– 6 –ode, whereas in the LG mode, these values were 0.60 mV/fC and 0.65 mV/fC, respectively . Thelower panels show the residuals between the data and fitting lines. Linearity is maintained with ±
10% integral nonlinearity up to ±
100 fC in the HG mode, while that extends to ± Figure 6 . Dynamic ranges of a typical readout channel in different gain modes. The lower panels show theresidual between the data and linear functions. The baseline is subtracted from the peak pulse height.
All the noise generated inside the amplifier is calculated as a quantity that is then converted into anequivalent noise charge (ENC), which is the noise generated at the input. The ENC is given by thefollowing formula:
ENC ( electron ) = V noise , rms ( mV ) Conversion gain ( mV / fC ) × . × − ( fC ) . Figure 8 shows the detector capacitance C det versus the corresponding ENC values. For comparison,the simulation result is overlaid in the figure. To improve the noise performance, on-chip ESDprotection diodes were not included in the analog inputs. The voltage noise is proportional to thedetector capacitance, and the ENC in the HG mode was measured as 2695 ± e − at C det =
300 pF.By comparing our results with the simulation value of 2361 e − , we can confirm that the performance– 7 – igure 7 . Gain variation in the HG mode. is very close to the simulation value, although there is about 13% offset at C det =
300 pF. Possiblecauses of the noise offset are the bonding wire and PCB trace capacitance due to the mounting ofthe ASIC on the evaluation board and the ground bounce due to a single-supply configuration, i.e. ,0/1.8 V. Based on these considerations, we expect to be able to improve the performance of theASIC in the next experiment and design. The ENC in the LG mode was measured as 37200 ± e − at C det =
300 pF with a noise slope of 5.41 e − /pF. Since the expected value is 36913 e − , weconcluded that the overall performance at RT are in agreement with the simulation models providedby the vendor. Moreover, the measured value is lower than the requirement of 64000 e − in the LGmode.The typical ionization signal for 1 MIP in the LAr-TPC of 10 fC, corresponding to 94000 e − ,is expected based on recent studies at the large LAr-TPC demonstrators [8]. The ENC of2700 e − achieves S/N = 23, and thus, the ASIC performance is considered to have reached thelevel of practical application if the RT performance can be kept at the LAr temperature. The dataprocessing architecture in LArTPCs to handle the analog outputs from all channels is currentlyunder discussion. Two options exist: either using external ADCs in parallel or on-chip ADCscombined with sparse readout. Since the number of readout channels is expected to be O( ) for a O(
10 kt ) detector, it is desirable to reduce the number of feedthrough lines running from the insideto the outside of the LAr cryostat. From this perspective, we will consider a circuit that consists ofboth analog and digital processing parts by optimizing the deep Nwell option of the current 180 nmCMOS technology. – 8 – igure 8 . The equivalent noise charge (rms) as a function of detector capacitance. Data and simulation areshown in red and blue, respectively. Figure 9 shows the experimental setup operated at the LAr temperature of ≈ -185 ◦ C. Since thefeed-through terminal of the cryostat limits the number of cable connections, we chose directimmersion of the electronics in a Dewar vessel filled with liquid argon. To avoid thermal stress onthe FPGA board, we separated the GoSHIK board from the ASIC, soaking only the SIRONEKOboard in liquid argon. Supply powers, test pulses, and monitor lines were directly connected withribbon cables. The bias voltages, which were tuned with trimmer potentiometers at RT, were alsoprovided by external power supplies. The direct immersion approach provides an easy-to-accessenvironment to the ASIC, although is subjects the ASIC and mounted components to harsh thermaland mechanical stresses. In this experiment, the temperature can be reduced to that of liquid argoninstantaneously, removing any time restrictions.
In the LAr temperature, we confirmed that the circuit could not be operated under the same biasconditions as the RT environment. By optimizing the bias settings we succeeded in obtaining analogoutputs; however, the conversion gain decreased and the noise level severely deteriorated. Suchdeterioration was not observed at RT in the Dewar. The baseline fluctuation was about 120 mV,while the peak height was about 530mV for an input charge of 40 fC. Compared with the RTresult, the gain decreased by about 40%. In order to specify the cause of this issue, we used thetime-averaging function of the oscilloscope and compared the waveforms at the RT and with thesimulation. The simulation methodology is discussed in the next section.– 9 – igure 9 . Experimental setup for the LAr temperature operation (left). Only the ASIC, i.e. , the SIRONEKOboard, was directly immersed in the LAr (right).
Figure 10 shows the time-averaged waveforms at RT and the LAr temperatures with an inputcharge of -40 fC and C det =
300 pF. Compared with the RT results, not only the conversion gain,but also the peaking time was clearly affected by the temperature; there was an increase of 60% inthe peaking time. The conversion gain at LT was determined to be 6.6 mV/fC, while the peakingtime was about 1.6 µ s. This result was contrary to our expectations since the charge carrier mobilityin silicon generally increases with decreasing temperature, while the thermal noise decreases at thesame time in the LT environment. Figure 11 shows the dynamic range at the LAr temperature. Figure 10 . Time-averaged waveforms at RT and LT. Data and simulation are shown in red and blue,respectively. – 10 – igure 11 . Comparison of the dynamic range in the HG mode with C det = pF. The analog performance at RT satisfied the requirements from the experiments, however, furtheroptimization of the circuits and devices is clearly necessary for operation of circuits immersed inthe LAr. In this section, we discuss possible causes of the performance degradation at LT and aunique simulation methodology for reliable cold electronics.The gain and peaking time of the analog output are related to the operating points of thedevices. It is generally known that the threshold voltage of the transistors increases as temperatureis reduced, with a similar shifting-magnitude for n- and p-channel transistors, e.g. , approximately1 mV/K [16]. The SPICE parameters are supported at -40 ◦ C from the vendor; however, there arehurdles to extending this model down to the LAr temperature. Instead of modifying the individualtransistor parameters, we attempt to utilize the body effect by changing the substrate voltage. Thethreshold voltage, V th , of the transistor including the body effect is described with the Fermi potentialof bulk silicon Φ F with respect to the intrinsic Fermi level as V th = V th0 + γ ( p | Φ F + V SB | − p | Φ F |) , (5.1)where V th0 is the threshold voltage of the transistor at RT, V SB is the source-bulk potential difference,and γ is the body effect coefficient which typically lies in the range of 0.3 to 0.4 V / [17]. Thus,it is possible to mimic the threshold voltages at LT, simply by changing V SB without consideringprocess-dependent parameters. In the actual simulation, we separated the substrate nodes fromthe source voltages, applying the negative values from the source voltage V BS , n for n-channels andpositive values of V BS , p for p-channels (see Fig. 13 as a schematic example).– 11 –he simulated waveforms with various V SB are shown in the left of Figure 12. The top andbottom panels respectively show the outputs of the CSA and band-pass filter. As V SB increases, thebaselines at the CSA and band-pass filter outputs linearly shift from the RT condition, while thethe rising edge of the CSA simultaneously becomes slower. On the other hand, the peaking timebecomes longer and pulse height becomes lower. The threshold shift is estimated as 200 mV if weassume the LAr temperatures, and thus, the corresponding V SB is 0.88–1.35 V. Here we assumed2 Φ F = V SB = . g m of the input FET. The right of Figure 12 shows g m as a function of V SB . The rise time ofthe CSA ( t r , CSA ) is given as t r , CSA = C det g m + C L µ · g m , (5.2)where µ = C f C f + C det and C L is the load capacitance at the CSA output. We can see that the risetime of the CSA becomes larger as g m decreases. The peaking time and pulse height of the filtercan be explained as a consequence of the slow rising edge of the CSA. The decrease of g m occursdue to the decrease of the internal bias current, which flows 100 µ A at RT . The right side of Fig. 12shows the internal bias current as a function of V SB . As described in Section 2, we used a diode- andcurrent mirror- configurations as a bias generator. However, even if the IBIAS node is connected tothe supply power, the internal current deviates as temperature decreases due to the higher thresholdvoltage in the simple diode-configuration. As a result, the nominal 510 µ A for the input FET is notprovided properly, and consequently, the g m deteriorates as temperature decreases.To reduce the threshold shift at the LAr temperature, we considered two approaches. The firstis to apply a forward bias voltage, e.g. , 0.5 V, to the source substrate junction. The resulting forwardcurrent might be negligible at low temperature because of the decrease in the intrinsic carrierconcentration. This approach requires additional power supplies for substrate biasing, however, it iseasier to tune the bias current externally. The second approach uses a feedback-based current circuitproposed in [18]. Figure 13 shows a schematic of such bias circuit, based on the beta-multiplier.The addition of the resistor kills the closed loop gain, and the positive feedback system can be stableas long as its closed loop gain is less than one. The bottleneck of the circuit is that the gain ofthe loop increases as the size of resistor decreases. This pushes the feedback system closer to theinstability. If the resistor, for example, is bonded out off-chip to set the current, it is likely that thisbias circuit will oscillate, and thus, the circuit is basically self-biased with an on-chip resistor. Forcomparison, current output as a function of V SB is overlaid in the right of Fig. 12 in a dashed line.We can see that the internal 100 µ A is stably provided by this circuit.
We have newly developed the TPC readout chip in the 180 nm CMOS technology. The front-endASIC is targeted at dual-phase LAr-TPCs for neutrino experiments and NI µ -TPC for directional– 12 – igure 12 . (Left): Simulation waveforms (top: CSA, bottom: shaper) with a typical process corner anddifferent V SB values. The injected charge is 40 fC in the HG mode. The baseline offset is also caused by thethreshold shift. (Right): the transconductance of the input transistor (top) and internal reference bias current(bottom) as a function of V SB . V BS,n
AVSSAVDD
VBIAS2 VBIAS1VBIAS2VBIAS3VBIAS4 100 uA100 uA V BS,p V BS,p V BS,p V BS,p V BS,p V BS,n V BS,n V BS,n V BS,n V BS,n V BS,n V BS,n V BS,n V BS,n V BS,n V BS,p V BS,p V BS,p V BS,p V BS,p V BS,p
Unlabeled NMOS are W/L=50/2, andunlabeled PMOS are W/L=100/2 in unit of 180 nm.
M = 10M = 10M = 10M = 10
Figure 13 . Schematic of the improved bias circuit based on the beta-multiplier [18]. All substrate biases areseparated from supply powers for the body-effect simulation. – 13 –ark matter searches. We optimized the transistor parameters of the previous prototype chip, takingcare in the layout for low-noise performance. The ENC reached 2695 ±
71 e − (rms) for a 300 pFdetector capacitance with a noise slope of 3.09 e − /pF at RT. The dynamic range and shaping timesalso satisfy the experimental requirements. In the LAr temperature testing, we have acquired theanalog waveforms from the ASIC, however, the noise level unexpectedly deteriorated with a longershaping time. By comparing our results with the SPICE simulation, this issue was found to becaused by threshold voltage shifts of the transistors at LT. This work describes a unique simulationmethodology for reliable cold electronics, which utilizes the body effect to mimic the thresholdshifts. This method can be applicable to general cold electronics designs. Acknowledgments
This work was supported by KAKENHI Grant-in-Aids (16H02189, 26104005, 17H01134, 18K03684,19H05806), JSPS Bilateral Collaborations (Joint Research Projects and Seminars) program.
References [1] T. Ikeda, et al.,
Results of a directional dark matter search from the NEWAGE experiment , J . Phys.:Conf. vol. 1468 (2020) 012042.[2] K. Miuchi, et al., CYGNUS , J . Phys.: Conf. vol. 1468 (2020) 012044.[3] A. Badertscher, T. Hasegawa, T. Kobayashi, A. Marchionni, A. Meregaglia, T. Maruyama,K. Nishikawa and A. Rubbia, A Possible Future Long Baseline Neutrino and Nucleon DecayExperiment with a 100 kton Liquid Argon TPC at Okinoshima using the J-PARC Neutrino Facility, arXiv:0804.2111 [hep-ph], DUNE collaboration, R. Acciarri et al., Long-Baseline Neutrino Facility(LBNF) and Deep Underground Neutrino Experiment (DUNE), arXiv:1601.02984.[4] T. Tanimori et al.,
Detecting the WIMP-wind via spin-dependent interactions , P hys. Lett. B vol. 578 (2004) pg. 241–246.[5] F. Mayet et al., A review of the discovery reach of directional Dark Matter detection , P hys. Rept vol.627 (2016) pg. 1–49.[6] D.P. Snowden-Ifft, R ev. Sci. Instrum. vol. 85 (2014) 013303.[7] T. Ikeda, submitted for J INST arXiv:2004.09706.[8] I. De Bonis, et al., Technical Design Report for large-scale neutrino detectors prototyping and phasedperformance assessment in view of a long-baseline oscillation experiment, Tech. Rep. CERN-SPSC-2014-013. SPSC-TDR-004 (Apr 2014). URL https://cds.cern.ch/record/1692375 .[9] A. Badertscher, L. Knecht, M. Laffranchi, A. Marchionni, G. Natterer, P. Otiougova et al., C onstruction and operation of a Double Phase LAr Large Electron Multiplier Time ProjectionChamber, in Proceedings of the Nuclear Science Symposium, Medical Imaging Conference and 16thInternational Workshop on Room-Temperature Semiconductor X-Ray and Gamma-Ray Detectors(NSS/MIC 2008/RTSD 2008), Dresden, Germany, 19–25 October 2008, pp. 1328–1334,arXiv:0811.3384.[10] M. Nakazawa et al., “Prototype Analog Front-end for Negative-ion Gas and Dual-phase Liquid-ArTPCs”, Jour. Instr., vol. 14, T01008, 2019. – 14 –
11] K. Miuchi,
Performance of the TPC with Micro Pixel Chamber Readout: micro-TPC , I EEE Trans. Nucl. Sci. vol. 50 (2003) pg. 825–830.[12] Y. Giomataris, Ph. Rebourgeard, J.P. Robert, and G. Charpak,