Programmable System on Chip for controlling an atomic physics experiment
PProgrammable System on Chip for controlling an atomic physicsexperiment
A. Sitaram, a) G. K. Campbell, and A. Restelli b) Joint Quantum Institute, University of Maryland and National Institute of Standards and Technology, College Park,Maryland 20742, USA (Dated: 23 February 2021)
Most atomic physics experiments are controlled by a digital pattern generator used to synchronize all equip-ment by providing triggers and clocks. Recently, the availability of well-documented open-source developmenttools has lifted the barriers to using programmable systems on chip (PSoC), making them a convenient andversatile tool for synthesizing digital patterns. Here, we take advantage of these advancements in the designof a versatile clock and pattern generator using a PSoC. We present our design with the intent of highlightingthe new possibilities that PSoCs have to offer in terms of flexibility. We provide a robust hardware carrierand basic firmware implementation that can be expanded and modified for other uses.
I. INTRODUCTION
Laser-cooled atoms, ions, and molecules are interest-ing and dynamic systems to study, and are being usedto develop many quantum technologies. These technolo-gies include precise atomic clocks , quantum comput-ers and simulators , and quantum sensors . Experi-ments in atomic, molecular, and optical (AMO) physicsare often a combination of a large number of commercialor custom-made instruments from different sources andmanufacturers that need to operate synchronously andin a repeatable fashion. Synchronization is achieved byusing a specialized software suite to control a primarydigital pattern generator or clock device with determin-istic timing that sends trigger signals to the other hard-ware devices. The PulseBlaster by SpinCore , a com-mercial device based on a field programmable gate array(FPGA), is commonly used as a primary clock in manyAMO experiments and is compatible with many differ-ent software suites. Many university groups have alsodesigned custom-made devices based around a microcon-troller or an FPGA as their primary clock. Microcon-trollers combine processing power with many peripheralsfor interfacing directly with hardware, and have founduse in a wide variety of physics experiments . On theother hand, FPGAs provide versatility in modifying theoverall system architecture to accommodate changes infunctionality, although they require more expertise fordevelopment. Despite the steeper learning curve, FPGAshave become a common choice as a control device in manyphysics experiments and work extremely well to accom-modate more complex architectures, as well as modularones .Another approach for controlling experiments is to cre-ate a complete infrastructure of software and modularhardware that is designed with built-in timing synchro-nization. Two commercial examples of this approach are a) [email protected] b) [email protected] LabView, a systems engineering software that is com-patible with National Instruments hardware, and AR-TIQ by M-labs , which is also a complete infrastruc-ture of software and hardware. Some university researchgroups have also created complete architectures, basingtheir hardware designs off of FPGAs and designing cus-tom control software .While FPGAs can work well as a primary control de-vice for an experiment, microcontrollers offer a simplersolution for handling complex communications protocolssuch as USB (Universal Serial Bus) or Ethernet. Often, amicrocontroller is used in conjunction with an FPGA, ei-ther externally or instantiated within the FPGA . Analternative approach is to use a programmable system onchip (PSoC), which combines an FPGA and a high per-formance microprocessor on a single chip. This allowsimplementation of operating systems, advanced commu-nication protocols, and high level language interpretersin the microprocessor, leveraging the FPGA when hard-ware acceleration or control of dedicated peripherals isneeded. Previously, development using PSoCs has beenless accessible due to the baseline level of expertise re-quired, but recently, thanks to the diffusion and level ofmaturity of tools such as PetaLinux or Yocto Project for the generation of GNU/Linux images, PSoCs havebecome more widely adopted .We chose a PSoC architecture to design our 64-channelpattern generator and primary clock with the goal of ex-panding the capabilities of our ultracold strontium ex-periment. Our requirement, to have a large number ofchannels operating in parallel with fast (
100 ns resolu-tion) and deterministic timing, points towards an FPGAas the platform of choice; however, we also had the goalof handling most of the data communication protocolsusing high level abstraction languages, such as Python,to facilitate testing and future rapid development. Toachieve these goals, we take advantage of the PYNQ(Python Productivity for Zynq) infrastructure , a plat-form for the development of applications with the XilinxZynq series of programmable systems on chip based onGNU/Linux and Python. Our lab uses the LabscriptSuite of software to control our experiment, which uses a r X i v : . [ phy s i c s . i n s - d e t ] F e b a text and GUI approach to provide efficient experimen-tal control for atomic physics experiments and is basedon the Python programming language. We designed ahardware platform around a Microzed Zynq-7020 mod-ule (produced by Avnet) mounted on a custom carrierboard with four low-jitter input trigger lines and eightbreakout boards with eight channels each to route the 64output lines. The FPGA gateware is written in Verilogand System Verilog, and we used Xilinx native develop-ment tools in order to make use of the many verificationfeatures, such as complex testbenches for behavioral sim-ulation. In the next sections, we will describe the systemarchitecture as a whole, as well as describe the hardwareand firmware in detail. II. SYSTEM OVERVIEW
Fig. 1 illustrates the overall architecture of our design,which can be broken down into three blocks: our hostPC (or lab control computer), the Microzed-7020 mod-ule, and the carrier and breakout boards. The Microzedmodule contains the Xilinx PSoC and a series of addi-tional peripherals, of which we show only the most rele-vant to our project: the I/O connectors to interface withthe carrier board, 1 GB of synchronous dynamic randomaccess memory (SDRAM), and an Ethernet physical layerchip (PHY) used for communication with the host PC.The PSoC (Xilinx XC7Z020-1CLG400C ) is composedof the processing system (PS) and the programmablelogic (PL). The PS is a dual core ARM Cortex-A9, whilethe PL is an Artix-7 FPGA fabric with approximately85000 logic cells.The PYNQ ecosystem allows us to run Linux Ubuntuon the PS and is equipped with a Jupyter notebook serveraccessible from a remote machine browser as a means tointeract with the PL using a Python application pro-gramming interface (API). Through the API, the PLcan be accessed using extended multiplexed input/outputlines (EMIO) or an AXI-lite (Advanced eXtensible In-terface) channel that can be used to map configurationregisters in the PL to the operating system’s RAM. Ad-ditionally, the SDRAM external memory used by the op-erating system can be accessed using a direct memoryaccess (DMA) controller.The heart of our design is in the PL, where we imple-mented a state machine written in System Verilog whichreads instructions from RAM instantiated in the FPGAfabric. The RAM is limited to = 32768 instructions.To allow for a longer list of instructions, we have imple-mented a ping-pong memory controller that moves datafrom the external SDRAM to the PL RAM through theDMA channel. The state machine and ping-pong mem-ory controller will be discussed in further detail in Sec-tions IV B and IV C, respectively.In the PS, we wrote an application server in Python toreceive instructions from the host PC through a socketconnection, transferring them to the shared SDRAM FIG. 1. Overall schematic of the pattern generator. Forconvenience, we summarize acronyms used in the figure: PC(Personal Computer), API (Application Programming Inter-face), PHY (PhYsical interface), PSoC (Programmable Sys-tem on Chip), PS (Processing System), PL (ProgrammableLogic), AXI (Advanced eXtensible Interface), EMIO (Ex-tended Multiplexed Input/Output), DMA (Direct Mem-ory Access), RAM (Random Access Memory), I/O (In-put/Output), SDRAM (Synchronous Dynamic RAM). Ele-ments of the system we designed in detail are shown in gray,while the white blocks are the components and software thatare available as commercial modules, open-source libraries, orautomatic software generation tools. and initiating DMA transfers. The application server ispaired with a socket client running on the host PC, alsowritten in Python, which acts as a low-level API to inter-face the Labscript instrument driver with the Microzedmodule.The Microzed board plugs into a custom-designed car-rier board using MicroHeader connectors. The outputsignals are then routed through eight breakout boardsand are accessible via BNC (Bayonet Neill–Concelman)connectors. The carrier board and breakout board de-signs are described in Sec. III.
III. HARDWARE FEATURESA. Carrier Board
The carrier PCB (Printed Circuit Board) routes the64 digital output lines from the expansion connectors ofthe Microzed module (Amphenol ICC 61083-101400LF)to eight 20-pin rectangular connectors, which are usedto distribute the signals to the breakout boards usingribbon cables. Placement of the 20-pin rectangular con-nectors was determined to keep the difference in lengthbetween all traces below
12 mm . The resulting maximumdifference in propagation time between channels is only ≈
64 ps , which is well within the goals of our design. Thecarrier board also has four BNC connectors for introduc-ing input clock or trigger signals to the Microzed. In or-der to adapt arbitrary trigger and clock standards to theFPGA input standards, each BNC input is connected tothe analog front end circuit shown in Fig. 2(a). Input sig-nals are sent through a high speed comparator chip (AD-CMP552BRQZ ) with PECL (Positive Emitter-CoupledLogic) outputs. We set a threshold on the invertinginput of the comparator using a voltage divider filteredwith a . µ F capacitor, and we connect the coaxial in-put to a network of components (R1, R2, R3, C1, C2)that can be used to adapt a variety of AC (AlternatingCurrent) or DC (Direct Current) input waveforms. R1is used as jumper to select between DC and AC inputs.In the default DC-coupled configuration, R1 = andR3 =
50 Ω , making the input compatible with . and TTL (Transistor Transistor Logic) standards. For anAC-coupled configuration, R1 is not placed, C1 = . µ F to block DC signals, and the values, R2 =
294 Ω andR3 = . , set the input impedance to
50 Ω , main-taining an average voltage of .
85 V at the input of thecomparator. The carrier board also provides a . supply for the I/O banks of the PSoC with two high-efficiency micro DC-DC converters (XCL214 ), and asupervisor chip (STM6779LWB6F ) ensures that the re-quired power sequencing for the PSoC is respected . FIG. 2. Termination networks used to interface the FPGAlogics with external signals. (a) shows the circuit used for thefour digital inputs on the carrier board while (b) shows thecircuit used for the 64 digital outputs.
B. Breakout Boards
The eight breakout boards use a Texas Instruments oc-tal buffer (SN74S244DWG4 ) to drive TTL signalsthrough
50 Ω coaxial cables. The electrical schematic fora single channel is shown in Fig. 2(b). The ribbon cableconnecting the carrier board with the breakout boardhas an alternating pattern of GND lines and digital sig-nal lines, which prevents crosstalk and sets a character-istic impedance of
50 Ω . The ribbon cable also carries a . supply used for termination and a supply usedto power the octal buffer. The two
100 Ω resistors inFig. 2(b) terminate the single-ended line from the PSoCto a Thevenin equivalent of
50 Ω at half the logic supply.This type of termination is called split termination andis described on page 26 of the Xilinx UG471 user guide .Each output of the octal buffer has an internal impedanceof
25 Ω , and therefore a series resistance of
25 Ω (R4) isadded in order to bring the output impedance to a stan-dard value of
50 Ω . The additional DNP (do not place)resistor (R5) can be used in conjunction with a differentvalue for R4 to produce an arbitrary Thevenin equiva-lent output that maintains a
50 Ω impedance, allowingthe user to configure the outputs to different logic stan-dards. For example, the values R4 =
75 Ω and R5 =
100 Ω would reduce the output voltage by a factor of 2. Thecoplanar waveguide in Fig. 2(b) is designed with a tar-get impedance of
50 Ω using the Kicad PCB calculator FIG. 3. (a) Breakout board layout. Signals enter theboard through the 20-pin connector at the top. Meandershelp equalize electrical delays of all traces. (b) Stack-up ofthe PCB for the coplanar waveguide (c) Stack-up of the PCBfor the microstrip below the BNC connector. (d) Close-upperspective view of the circuit board layout. Figure is not toscale.
FIG. 4. Time Domain Reflectometry measurement of thebreakout board. The characteristic impedance of the BNCconnector and coplanar waveguide remain within of the
50 Ω target value. software.Fig. 3(a) shows how the eight coplanar waveguides arearranged on the breakout board. To prevent variations inthe timing delay across different output channels, we havematched the length of all 8 traces using meanders. Basedon the information provided by the PCB manufacturer(nominal relative dielectric constant (cid:15) r = 4.3), we de-signed the coplanar waveguide, as illustrated in Fig. 3(b),with a width W = .
46 mm , spacing between traces andtop-layer ground plane S = . , and separation fromtop-inner-layer ground plane H = .
24 mm . We choseedge-mount BNC connectors rated up to 4 GHz to mini-mize the characteristic impedance discontinuity from thePCB to the coaxial cables. For impedance matching,the connectors need to be soldered to a microstrip thatends at the edge of the PCB. However, to ensure an ad-equate mechanical strength for the connector’s centralpin soldering joint, the width of the microstrip must bemuch larger than the width W = .
46 mm of the copla-nar waveguide in Fig. 3(b). To allow for a wider sectionof the transmission line, we therefore remove the inner-top ground layer from under the central pin’s solderingpad, as shown in Fig. 3(c). Using the inner-bottom layeras the new ground plane, the distance from the trans-mission line is increased to H = .
26 mm . A nominal
50 Ω impedance is now obtained with W = .
29 mm andS = .
27 mm . A perspective view of the PCB layers isshown in Fig. 3(d).We verified the performance of the transmission linesand BNC launch by performing a time domain reflec-tometry (TDR ) measurement on the PCB. The resultof the meaurement is shown in Fig. 4, where we use thetechnique described in Ref. to measure the amplitudeof a reflected step signal to calculate the characteristicimpedance along a transmission line as a function of elec-trical delay. We first measure the response of a coaxialcable with an SMA (SubMiniature version A) connectorattached to a SMA
50 Ω termination. We then connectthe coaxial cable to our PCB board, while not powered, using a SMA to BNC adapter and compare the two TDRresponses. Four different sections can be distinguishedin the traces in Fig. 4: the SMA connector, the BNCadapter, the coplanar waveguide on the PCB, and theoutput buffer passive impedance. Apart from the outputbuffer, which shows a change of impedance compatiblewith a capacitive load, the maximum impedance varia-tion for the BNC connector and coplanar waveguide de-sign is below ≈ , limiting reflections below ≈ . IV. FIRMWARE DEVELOPMENTA. Communication
To communicate instructions to the PSoC, we open asocket server on the PS. We then wait for the TCP/IPclient on the lab computer to connect. Once the connec-tion is established, data is sent through the socket storedin a numpy array , which is mapped on a contiguoussection of SDRAM shared with the PL through a DMAcontroller. The data is then accessed by the PL and pro-cessed by the state machine as instructions in a 128 bitformat extension of the 80 bit long instruction formatused in the PulseBlaster . In case the connection is un-expectedly broken, we have implemented an algorithmfor the server to automatically refresh the same socketconnection, instead of creating a new one. This makesthe system robust against the interruption of the connec-tion without having to manually reset it. B. State Machine
To control the 64 TTL output channels, we have writ-ten a Mealy state machine in the programmable logicof the FPGA. In contrast with Moore state machines,Mealy state machines’ inputs directly affect the outputs,allowing for a lower-latency design. We wrote our statemachine in System Verilog to take advantage of special-ized features of the language, such as enumeration logicand the passing of structured data through design mod-ules. The state machine first fetches 128 bit instructionsfrom a 128x32768 RAM, mapped as shown in Fig. 5.There are five fields that make up the 128 bit instructionto the state machine: time delay (32 bits), data (20 bits)opcode (4 bits), flags (64 bits) and finally the remaining 8bits are reserved for future use. The state machine readsthe memory bank row by row. The opcode tells the statemachine which state to enter next, and the flags field des-ignates which output channels will be changed or affectedwith each instruction. The data contains any special in-formation specific to the current opcode. For example, ifthe state machine is being instructed to enter a loop, thedata would contain the number of loop iterations. Fi-nally, the ‘delay’ argument indicates how long the statemachine should wait before loading the next instruction. FIG. 5. Illustration of the memory in the FPGA. The memory is split into Bank 0 and Bank 1, each with 16834 instructions.The memory has a width of 128 bits. Each instruction contains 64 bits for the state of each of the flags, 4 bits for the opcode,20 bits for the data argument, and 32 bits for the time delay argument. The last 8 bits are left unused, but can be allocatedin the future.
The states that we have programmed in our state ma-chine are shown in Table I, along with the accompanying‘data’ field. To facilitate integration with Labscript, wechoose an instruction set that is mostly compatible withthe one of the Pulseblaster, which is extensively usedwithin the Labscript codebase (we did not implementnested loops, as they are not used in Labscript).
State Instruction Data Function
TABLE I. List of states that was programmed in the statemachine with associated data field and description of the func-tion performed. The state numbering corresponds to the as-sociated opcode.
C. Ping-Pong Memory
The state machine described in the previous sectionis designed to read instructions from a 32768-instructionstatic memory. To increase the available memory, we usethe 32768-instruction space as a cache memory and di-vide it into two banks with = 16384 instructions each:Bank 0 and Bank 1, as shown in Fig. 5. We then im-plement a ping-pong memory controller to automaticallyupdate the content of the memory by requesting directmemory access (DMA) to a large shared contiguous por-tion of the SDRAM, which has space for up to 8192000instructions. The algorithm for the ping-pong memorycontroller is shown in Fig. 6(a). The controller begins bytransferring 16384 instructions from SDRAM into Bank 0of the PL RAM and setting a register called “last_bank”equal to 1. The main state machine then begins execut-ing instructions from RAM, starting from Bank 0, whilethe ping-pong memory controller constantly monitors thememory address. Each time the memory address is not inthe bank identified by the register “last_bank”, the pre-viously accessed bank is refreshed with new data fromthe SDRAM and the value of “last_bank” is updatedwith the identifier of the currently accessed bank. Set-ting “last_bank” equal to 1 when the state machine startscauses Bank 1 to be updated immediately after Bank 0 assoon as the state machine accesses the memory. The PLRAM is a dual port memory that can be independentlyaddressed from two different clock domains. Thus, thestate machine controlling the 64 TTL outputs does notneed to be synchronous with the rest of the PL and withthe PS. The ping-pong memory controller and DMA en-gine are clocked by the PS, while the state machine can beoptionally clocked from one of the PLLs (Phase LockedLoop) available in the PL fabric that can be locked to anexternal reference connected to one of the four availableBNC inputs.The automatic RAM refresh implemented by the ping-pong memory controller can pose a problem if certain in- FIG. 6. Bank switching and compiler check algorithms forthe ping-pong memory controller. (a) The system beginsby loading bank zero and setting the “last_bank” to Bank1. From there, the system consistently checks the memoryaddress of the state machine to determine whether it hasswitched banks in the memory. If it has switched banks,it changes “last_bank” and loads the other bank of memorywith new instructions. (b) Checks performed during com-pilation to avoid memory underflow. The logic expressionsmem_addr % > − and mem_addr % = 2 − check, respectively, if mem_addr is mapped to the last twoslots or the last slot in the memory bank (% is the MOD operator). structions span over two banks, such as
LOOP/END LOOP,BRANCH, JSR/RTS . For example, if a loop is started in thefirst bank, but ends in the second bank, since the firstbank is updated with new instructions while the secondbank is running, the system will no longer have the ini-tial loop instruction to refer back to. The compiler mustbe aware of this type of memory bank underflow or over-flow and be able to resolve them by altering the order andnumber of instructions, without changing the final behav-ior at run time. In the current Labscript driver, there isonly one instance where underflow can happen: when thecomplex instruction called “reps” is translated into eithera
LOOP immediately followed by an
END LOOP instruc- tion or a series of
LOOP, LONG DELAY, END LOOP . To pre-vent memory underflow, we have implemented checks inthe code while the program is compiling. The algorithmis illustrated in Fig. 6(b). When a
LOOP opcode is found,the system checks if either the instruction is mapped onthe last instruction of a bank or if it is mapped on thesecond to last and is immediately followed by a
LONG DE-LAY instruction. In these cases, it inserts additional
CON-TINUE instructions to ensure that the
LOOP instructionis moved to the beginning of the next bank. To ensurethat the insertion does not modify the original timing,the field ‘delay’ in the
LOOP instruction is reduced bythe duration of the inserted
CONTINUE instructions.
V. DISCUSSION
The PSoC-based primary clock device, that we havecreated for controlling AMO physics experiments, is eas-ily integrated with the Labscript Suite. The hardwareprovides 64 buffered digital outputs for controlling otherhardware devices and also 4 input trigger channels. Theprinted circuit board design ensures signal integrity andminimal crosstalk between channels. Our firmware de-sign implements a state machine written in System Ver-ilog and a ping-pong memory controller that allows theexecution of a large number of instructions (exceeding8192000). The system is currently being used to runthe entire experiment in our lab, providing triggers fordigital to analog coverters (DAC), digital direct synthe-sizers (DDS), mechanical shutters, and many other in-struments.According to the Synthesis tools timing reports themaximum frequency the state machine can operate at is
104 MHz , and it is currently clocked at
100 MHz . There-fore, the current timing resolution is
10 ns , although usingserializers in the PL fabric would allow timing resolutionsdown to . The versatility of the platform also allowsfor other modifications, such as the possibility to addadditional instructions to the state machine. For exam-ple, an additional instruction could initiate a train of aspecific number of pulses with an adjustable duty cycleand period using a single instruction, rather than usingloops. Other extensions of the instruction set could al-low for conditional branching, which has already beenshown to be useful in ion trapping experiments . Fur-ther modifications to the design might include networksecurity protocols and encryption for data transmission,which we have not included since our setup is runningon an isolated network. A possible use of the systemwe have considered, and have extensively taken advan-tage of during testing, is its capability to run scripts di-rectly from the local Jupyter notebook server. With theJupyter web interface, a remote computer is not neces-sary for the generation of patterns, and the device can beused as a stand-alone testbench digital pattern generator.Our PSoC-based primary clock device has the capabil-ity to be integrated with many experimental setups withminimal modification, and the whole design is availableonline . ACKNOWLEDGEMENTS
We thank Daniel Barker, Qi-Yu Liang, and Peter Elgeefor their careful reading of the manuscript. This workwas partially supported by the NSF through the PhysicsFrontier Center at the Joint Quantum Institute.
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