Structure-Based Local Search Heuristics for Circuit-Level Boolean Satisfiability
aa r X i v : . [ c s . A I] S e p Structure-Based Local Search Heuristics forCircuit-Level Boolean Satisfiability
Anton Belov ⋆ and Matti J¨arvisalo ⋆⋆ Complex and Adaptive Systems Laboratory, University College Dublin, Ireland Department of Computer Science, University of Helsinki, Finland
Abstract.
This work focuses on improving state-of-the-art in stochastic localsearch (SLS) for solving Boolean satisfiability (SAT) instances arising from real-world industrial SAT application domains. The recently introduced SLS methodCRS AT has been shown to noticeably improve on previously suggested SLS tech-niques in solving such real-world instances by combining justification-based lo-cal search with limited Boolean constraint propagation on the non-clausal for-mula representation form of Boolean circuits. In this work, we study possibilitiesof further improving the performance of CRS AT by exploiting circuit-level struc-tural knowledge for developing new search heuristics for CRS AT . To this end,we introduce and experimentally evaluate a variety of search heuristics, many ofwhich are motivated by circuit-level heuristics originally developed in completelydifferent contexts, e.g., for electronic design automation applications. To the bestof our knowledge, most of the heuristics are novel in the context of SLS for SATand, more generally, SLS for constraint satisfaction problems. Stochastic local search (SLS) [11] is an important paradigm which facilities finding so-lutions to various kinds of hard computational problems via searching over a declarativeformulation of the problem at hand. It has been recognized that one possibility to pushfurther the efficiency of SLS techniques is to develop search techniques that exploit the structure of constraint satisfaction problems. Indeed, various structure-exploiting SLSmethods have been developed (among others) for generic constraint satisfaction prob-lems (CSPs; for examples see [1,2,18,10]) and Boolean satisfiability (SAT; for examplessee [16,20,21,17,19,14,13,22,4,5]).This work focuses on developing efficient structure-exploiting SLS techniques forSAT. In more detail, we study techniques that are aimed at industrially relevant (or,as termed in the latest 2011 SAT Competition, application ) instance classes. The mosteffective methods for solving random
SAT instances are based on SLS. Furthermore, re-cent advances in SLS for crafted
SAT instances has resulted in an SLS method winningthe satisfiable crafted instance category of the 2011 SAT Competition . In contrast, onindustrial instances the current SLS methods are often notably inferior to the dominantconflict-driven clause learning (CDCL) SAT solvers. ⋆ Partially supported by SFI PI grant BEACON (09/IN.1/I2618). ⋆⋆ Financially supported by Academy of Finland under grant 132812. Results are available at http://satcompetition.org/2011/. o the best of our knowledge, currently the best performing SLS method aimed atindustrial SAT instances is CRS AT [5,6]. Instead of working on the rather low conjuc-tive normal form (CNF) level, CRS AT searches for a solution directly on the level ofarbitrary propositional formulas, relying on the compact representation form of Booleancircuits for a succinct way of representing propositional formulas. Furthermore, insteadof relying on restricting search to input variables, as often has been proposed [16,20,21,17,19],CRS AT is based on the justification-based circuit-level SLS approach [14,13], search-ing over the whole subformula structure, and incorporates a limited form of directedcircuit-level Boolean constraint propagation to further exploit structural aspects of theinput formulas [5].We have recently shown that CRS AT can be further improved by incorporating astructure-based heuristic for focusing search steps. This resulted in the depth-based variant of CRS AT [6]. The depth-based heuristic has interesting fundamental prop-erties, including the fact that CRS AT remains probabilistically approximately com-plete (PAC) [12] even when focusing search via the heuristic. Contributions
The success of the depth-based search heuristic suggests that circuit-level structural properties of SAT instances can indeed be exploited to further im-prove SLS. Motivated by this, in this work we develop and experimentally study awide range of novel structure-based SLS search heuristics, focusing on CRS AT . Weprovide a systematic large-scale study of the proposed structure-based heuristics. Werelate the heuristics to the depth-based heuristic studied in detail in [6], with the aimof developing further understanding on what are the underlying properties that makethe depth-based search work in practice. Furthermore, we investigate whether related(or even completely different) structural properties result in even more effective heuris-tics. Analysis of the experiments reveals various interesting observations on the type ofstructural properties of circuits result in effective search heuristics.Finally, as a future motivation for the studied heuristics, we are interested in ex-tending the CRS AT approach, combining justification-based search over logical com-binations of constraints and exploiting limited constraint propagation, to more genericclasses of constraint satisfaction problems (CSPs) for which local search is a very viablealternative [1,2,18,10]. The development of good structure-based search heuristics forthe circuit-level is directly applicable for the logical combinations of more high-levelconstraints, where the logical combinations can be viewed as circuits. Organization
Key definitions and concepts related to Boolean circuit satisfiability arereviewed as necessary preliminaries in Sect. 2. Sect. 3 is dedicated to presenting theCRS AT circuit-level SLS algorithm for which this work develops structure-based searchheuristics. The heuristics are introduced in Sect. 4. Before conclusions (Sect. 6), resultsof an extensive empirical evaluation on the effectiveness of the structure-based heuris-tics are presented in Sect. 5. A Boolean circuit over a finite set G of gates is a set C of equations of the form g = f ( g , . . . , g n ) , where g, g , . . . , g n ∈ G and f : { , } n → { , } is a Booleanunction, with the additional requirements that (i) each g ∈ G appears at most onceas the left hand side in the equations in C , and (ii) the underlying directed graph h G, E ( C ) i , where E ( C ) = {h g ′ , g i ∈ G × G | g = f ( . . . , g ′ , . . . ) ∈ C } , is acyclic.If h g ′ , g i ∈ E ( C ) , then g ′ is a child of g and g is a parent of g ′ . For a gate g , thesets of its children (i.e., the fanin of g ) and parents (i.e., the fanout of g ) are denotedby fanin ( C, g ) and fanout ( C, g ) , respectively. The descendant and ancestor relations fanin ∗ and fanout ∗ are the transitive closures of the child and parent relations, respec-tively. If g = f ( g , . . . , g n ) is in C , then g is an f -gate (or of type f ). A gate with nochildren (resp. no parents) is an input gate (resp. an output gate ). The sets of input gatesand output gates in C are denoted by inputs ( C ) and outputs ( C ) , respectively. A gatethat is neither an input nor an output is an internal gate . Typical gate types include NOT ( NOT ( v ) is iff v is ) and AND ( AND ( v , v ) is iff both v and v are ).An (truth) assignment for C is a (possibly partial) function τ : G → { , } . Acomplete assignment τ for C is consistent if τ ( g ) = f ( τ ( g ) , . . . , τ ( g n )) for each g = f ( g , . . . , g n ) in C . When convenient we write h g, v i ∈ τ instead of τ ( g ) = v .The domain of τ , i.e., the set of gates assigned in τ , is denoted by dom ( τ ) . We say thattwo assignments, τ and τ ′ , disagree on a gate g ∈ dom ( τ ) ∩ dom ( τ ′ ) if τ ( g ) = τ ′ ( g ) .For a truth assignment τ and set of gates G ⊆ dom ( τ ) , let flip ( G, τ ) denote the truthassignment obtained by changing the values of the gates in G , and leaving the rest of τ unchanged.A constrained Boolean circuit C α consists of a Boolean circuit C and an assignment α for C . Each h g, v i ∈ α is a constraint , and g is constrained to v if h g, v i ∈ α .A complete assignment τ for C satisfies C α if (i) τ is consistent with C , and (ii) itrespects the constraints: τ ⊇ α . If some assignment satisfies C α , then C α is satisfiable .A circuit that is not satisfiable is unsatisfiable . Without loss of generality, we assumethat constraints are imposed only on output gates.The restriction τ | G ′ of an assignment τ to a set G ′ ⊆ G of gates is defined as {h g, v i ∈ τ | g ∈ G ′ } . Given a gate equation g = f ( g , . . . , g n ) and a value v ∈{ , } , a justification for the pair h g, v i is a partial assignment σ : { g , . . . , g n } →{ , } to the children of g such that f ( τ ( g ) , . . . , τ ( g n )) = v holds for all exten-sions τ ⊇ σ . That is, the values assigned by σ to the children of g are enough toforce g to take the consistent value v . For example, the justifications for h g, i , where g = AND ( g , g ) , are {h g , i} , {h g , i} , and {h g , i , h g , i} , out of which the firsttwo are subset-minimal . A gate g is justified in an assignment τ if it is assigned, i.e. τ ( g ) is defined, and (i) it is an input gate, or (ii) g = f ( g , . . . , g n ) ∈ C and τ | { g ,...,g n } is ajustification for h g, τ ( g ) i . We denote the set of unjustified gates in an assignment τ by unjust ( C α , τ ) . CRS AT is an SLS-based SAT algorithm for Boolean circuits that operates directly oncircuit structure – that is, without the conversion to CNF. The algorithm was first de-scribed in [5] and was subsequently analyzed theoretically and improved in [6]. In thissection we provide a high-level overview of the algorithm, and refer the reader to [5,6]for additional details.RS AT is based on the justification-based [14,13] approach to circuit-level SLS.In this approach, the circuit is traversed from the outputs to inputs, and the values ofthe internal gates are adjusted using local information in an attempt to eliminate allunjustified gates. CRS AT combines a weakened version of justification-based SLS withso called limited forward propagation – a restricted form of circuit-level Boolean con-straint propagation, described in what follows.Pseudo-code for CRS AT is presented as Algorithm 1. First, a complete extension ofa random value assignment to inputs ( C α ) is constructed, i.e., the value of each uncon-strained internal gate is set consistently with the values of its children. Then, as long as unjust ( C α , τ ) is not empty (i.e., τ is not a satisfying assignment), the algorithm heuris-tically selects an unjustified gate g (line 6; we will discuss gate selection heuristics inthe next section in detail). Once an unjustified gate g is chosen, the algorithm selectsa justification σ for h g, τ ( g ) i (lines 7- 13) and performs a search step . The latter con-sists of (i) flipping the values of gates on which σ and τ disagree (line 15), followed by(ii) propagating the consequences of the flip towards the outputs of the circuit (line 16). Algorithm 1
Generic CRS AT ( C α , wp , cutoff ) Input: C α – constrained Boolean circuit wp – noise parameter ,i.e., probability of random walk cutoff – cutoff, i.e., maximum number of steps Output: status – SAT if a satisfying assignment for C a is found, UNKNOWN otherwise τ – a satisfying assignment for C α if found, ∅ otherwise1: τ ← a complete extension of a random assignment to inputs ( C α ) steps ← while steps < cutoff do if unjust ( C α , τ ) = ∅ then return h SAT , τ i g ← a heuristically selected gate from unjust ( C α , τ ) Σ ← the set of justifications for h g, τ ( g ) i with-probability wp do σ ← random element of Σ ⊲ random walk10: otherwise σ ← a random justifications from those in Σ that minimize12: the number of unjustified gates after the step ⊲ greedy downward move13: end with-probability G ← set of gates in σ that disagree with τ τ ← flip ( G, τ ) ⊲ flip16: τ ← LBCP-F
ORWARD ( C α , G, τ ) ⊲ limited forward propagation17: steps ← steps + 1 return h UNKNOWN , ∅i The justification σ used to make a step can be selected from the set Σ of all justifica-tions for h g, τ ( g ) i either at random (with probability wp ), or greedily with the objectiveof minimizing the number of unjustified gates after the step. Note that taking Σ to be aset of subset-minimal justifications results in good performance in practice; this is alsohow our current implementation works.he forward propagation procedure LBCP-F ORWARD is presented as Algorithm 2.It uses a priority queue Q of gates (with no duplicates) that allows to query the small-est gate according to a topological order in constant time . Essentially, the procedureimplements a circuit-level Boolean constraint propagation algorithm, except that (i) thevalues are propagated only towards the outputs of the circuit, and (ii) propagation alongeach path stops immediately when an unjustified gate becomes justified; hence it im-plements limited forward propagation . The addition of limited forward propagation tojustification-based SLS results in multiple orders of magnitude speed-ups on industrialSAT instances [3]. Algorithm 2
LBCP-F
ORWARD ( C α , G , τ ) Input: C α – constrained Boolean circuit; G – a set of gates whose value changes are to be propagated. τ – an assignment for C a ; Output: τ ′ – an assignment for C α which is a result of limited forward propagation of theassignment τ | G .1: τ ′ ← τ Q . ENQUEUE ( G )3: while ¬ Q . EMPTY do g ← Q . POP FRONT if g ∈ G then ⊲ g is one of the original gates6: Q . ENQUEUE ( fanout ( g ) )7: else if g ∈ unjust ( C α , τ ′ ) \ dom ( α ) then ⊲ g unconstrained and unjustified9: τ ′ ← flip ( { g } , τ ′ ) Q . ENQUEUE ( fanout ( g ) )11: return τ ′ It comes as no surprise that the effectiveness of CRS AT depends critically on theway the gates are selected for justification during the search (Line 6 of Algorithm 1).A good selection heuristic focuses search to the most important gates in terms of sat-isfiability. On the other hand, if a too deterministic (focused) selection procedure isused, the search may not converge into a satisfying assignment. In [6] we showed thatthe efficiency of CRS AT can be significantly improved by focusing the search usinga structure-based gate selection heuristic which takes into account the depth of the se-lected gates. In the next section we describe a number of additional structural propertiesof gates and propose a number of gate selection heuristics based on these properties. AT In this section we introduce a number of heuristics for selecting of the unjustified gateto justify at each search step in the main loop of CRS AT (line 6 of Algorithm 1). Theunderlying idea is that these heuristics should be able to take into account the structural Recall that a topological order on the set of gates in a circuit is any strict total order < thatrespects the condition “if g ∈ fanin ( g ) , then g < g ” roperties of the constrained Boolean circuit at hand, and focus the search on the gatesthat are deemed important based on these properties. Additionally, we must aim at effi-ciently computable heuristics, as the main loop may be executed millions of times in atypical run of the algorithm (although, in contrast to typical SLS algorithms, most of thecomputation effort in CRS AT is attributed to the execution of forward propagation, andhence we can afford slightly more expensive computations than usual SLS heuristics).We now give a listing of the initial set of gate properties, with intuition on whythese properties may be interesting. We then describe the corresponding gate selectionheuristics, and, in the next section, present the results of the preliminary empirical eval-uation of these heuristics. The analysis of the results will lead us to the development ofadditional heuristics, which will be described and analyzed in Sect. 5. Depth: depth ( C, g ) , where the depth of a gate g in C is depth ( C, g ) = (cid:26) if g ∈ outputs ( C α )1 + max { depth ( C, g ′ ) | g ′ ∈ fanout ( C, g ) } otherwise.The importance of gate depth for CRS AT was justified theoretically and confirmedempirically in [6]. The key aspect is that selection of gates with high depth drivesthe algorithm close to the inputs of the circuit, thus allowing the algorithm to ex-plore the space of assignments to input gates faster. The depth of all gates in C can be computed in O ( | C | ) time (where | C | denotes the number of gates in C ), andstored for constant time retrieval. FO: | fanout ( C, g ) | Gates with large fanout size are in a sense more influential than the rest. Intuitively,by forcing CRS AT to justify these gates, the truth values of these critical parts ofthe circuit are fixed first, which may result in many of the other gates’ values to beset by forward propagation. The fanout size of a gate is retrieved in constant time. TFO: | fanout ∗ ( C, g ) | This is also a measure of the influence of the gate in the circuit: intuitively, thelarger the size of the transitive fanout , the more influence the gate’s value has ontransitively justifying the output constraints of the circuit via forward propagation.The computation of the size of the transitive fanout of a gate requires O ( | C | ) in theworst-case (although typically only a fraction of gates in C have to be evaluated). TFI: | fanin ∗ ( C, g ) | The size of the transitive-fanin of a gate g can be considered an estimate of thenumber of search steps required to justify all gates in the sub-circuit rooted at g .This measure is also related to the size of the interest set used as an objectivefunction in justification-based SLS algorithm BC SLS [14,13]. The computationof the size of the transitive fanin of a gate requires O ( | C | ) in the worst-case. CC: CC ( C, g, τ ( g )) , where the SCOAP (Sandia Controllability and Observability Anal-ysis Program) combinational controllability measure [9] CC is defined as follows: Here one should notice that driving the search towards input gates in justification-based searchis different from the idea of restricting the flips to input gates as in [16,20,21,17,19] due to theconceptual differences of these approaches. C ( C, g,
0) = (cid:26) if g ∈ inputs ( C )1 + min g ′ ∈ fanin ( C,g ) CC ( C, g ′ , if g is an AND -gate, CC ( C, g,
1) = (cid:26) if g ∈ inputs ( C )1 + P g ′ ∈ fanin ( C,g ) CC ( C, g ′ , if g is an AND -gate.Given a gate g and its current value v g , SCOAP aims to provide a measure of howdifficult it is to satisfy the sub-circuit rooted at g given that g is constrained to v g (i.e., to control the value v g at g ). Originally, SCOAP was used as a combinationaltestability measure. For our purposes, SCOAP intuitively provides a measure ofhow difficult it is to transitively justify the output constraints of a circuit. Due tothe fact that we apply And-Inverter graphs (AIGs) as benchmark instances in thispaper, the definition is restricted to AND -gates only. However, the definition can benaturally extended to other gate types.Here one should notice the original definition of SCOAP assigns for
NOT -gates(negations) the value of the gate’s child incremented by one . In contrast, here we dono increment such values, but instead implicitly skip
NOT s in the following sense.In case g = NOT ( g ′ ) , all gates in fanout of g ′ are included in fanout of g ′ insteadof g . This is due to the fact that negations (inverters) are handled implicitly in thejustification steps and forward propagation performed by CRS AT , and hence the CC value assigned to each NOT -gate equals the value assigned to the gate’s child.Note that SCOAP controllability measures for all gates in C can be computed in O ( | C | ) time. CO: CO ( C, g ) , where the SCOAP combinational observability measure [9] is definedas follows: CO ( C, g ) = (cid:26) if g ∈ outputs ( C )1 + min g ′ ∈ fanout ( C,g ) CCO ( C, g ′ , g ) otherwise,where for an AND -gate we have
CCO ( C, g ′ , g ) = CO ( C, g ′ ) + X g ′′ ∈ fanin ( C,g ′ ) \{ g } CC ( C, g ′′ , . As in CC , we implicitly skip NOT s in the definition. This measure attempts to cap-ture how difficult it is to observe a specific value for a gate given the output con-straints; in other words, how likely is it that the value is part of a minimal justifica-tion that is transitively consistent with the output constraints. The measure can becomputed for all gates in C in O ( | C | ) time. Flow: flow ( C, g ) , where the output flow value of a gate g in C is flow ( C, g ) = if g ∈ outputs ( C ) X g ′ ∈ fanout ( C,g ) flow ( C, g ′ ) | fanout ( C, g ′ ) | otherwise.In other words, we compute a total flow value for each gate by pouring a unitquantity flow down from the output gates of the circuit. Here it is important tootice that the definition of flow implicitly skips NOT -gates. This flow-based ideawas first evaluated in [15] as a heuristic for restricting the set of decision variables inCDCL solvers. Our intuition is that, if a large total flow passes through a particulargate, the gate is globally very connected with the constraints in τ , approximatingin a sense the number of possible paths for forward propagation, and thus g wouldhave an important role in the satisfiability of the circuit.Each of the structural properties presented above gives rise to a pair of gate selectionheuristics: for a given property f ( C α , g, τ ) , one heuristic selects at random a gate from argmax g ∈ unjust ( C α ,τ ) f ( C α , g, τ ) . We will refer to this heuristic as a max-variant , f -max , of the heuristic based on f .And, a dual heuristic, the min-variant , f -min , selects at random a gate from argmin g ∈ unjust ( C α ,τ ) f ( C α , g, τ ) . Thus, we have 7 pairs of dual heuristics, and the baseline heuristic
Rand that simplyselects a random gate from from unjust ( C α , τ ) – this is the heuristic used in the originalpaper on CRS AT [5].We now note that some of the presented structural measures of gates are in partscorrelated (either positively or negatively) with gate depth (these are TFO , TFI , CC , CO ), while others ( FO , Flow ) are not. The reason that we pay a particular attention tothe depth is that we know that the
Depth-max heuristic is very effective [6]. As such,when we evaluate the heuristics based on the properties that are positively correlatedwith depth ( depth-friendly heuristics) we are interested in detecting improvements over
Depth-max . Such an improvement would suggest that another, perhaps more funda-mental property, is at play in CRS AT -style circuit SLS. Furthermore, the duals of depth-friendly heuristics are expected a priori to perform poorly. In evaluating the heuristicsthat are not correlated with depth ( depth-agnostic heuristics), we are also interested indetecting significant differences in performance on some classes, or even on particularproblem instances. Such differences would suggest that depth-agnostic heuristics mightbe used as secondary heuristics in CRS AT (e.g. for tie-breaking).To summarize, the following heuristics are the primary targets of the empirical eval-uation and analysis presented in the next section: – Baseline : Rand and also
Depth-max . – Depth-friendly : TFO-max , TFI-min , CC-min (small controllability value meansthe gate is easy to control, and hence intuitively close to inputs),
CO-max (largeobservability value means the gate is difficult to observe, and hence intuitively farfrom outputs). – Depth-agnostic : FO-min , FO-max , Flow-min , Flow-max . In order to provide an objective empirical comparison of SLS solvers, the well-knownSLS textbook by Hoos and St¨utzle [11] suggests a procedure for finding near-optimaloise (the setting of the parameter wp in Alg. 1) by essentially binary searching for thenoise values for each individual instance and solver to be evaluated. While full binarysearch is computationally infeasible given the vast number of benchmark instances usedin our experiments and, on the other hand, the computational resources available to us,we applied the following approximation of the Hoos-St¨utzle scheme. Noise was opti-mized for each solver and instance individually based on 25 tries using a timeout of 200seconds per try (with no limit on the number of steps), at noise values 0.05, 0.1, 0.2,0.3, 0.4, 0.5. The noise with highest success rate (primary criterion) and best mediantime (secondary criterion) was selected. In cases where there were two or more optionsranked best using both of these criteria, a random candidate among those options waspicked. Note that the benchmark-class based noise optimization, which is computation-ally cheaper, is often insufficient on industrial application benchmarks. For example,among 61 solved instances of one of the benchmark classes described below ( sss-sat-1.0 ) we found 10 instances to have a near-optimal noise value, wp no , of 0.05, 10 with wp no = 0 . , 14 instances with wp no = 0 . , 9 instances with wp no = 0 . , 9 instanceswith wp no = 0 . and 9 instances with wp no = 0 . .The reported CPU times and number of steps for each instance are the median CPUtime (in seconds) and the median number of search steps with the best noise settingover 25 tries for the experiments summarized in Fig. 1 and 3, and over 100 tries forthe experiments summarized in Fig. 2. . The experiments were performed on an HPCcluster, each node of which runs on a dual quad-core Xeon E5450 3-GHz with 32 GBof memory. As benchmarks, we considered over 650 And-Inverted circuits (AIGs, that is, con-strained Boolean circuits in which gate types
AND and
NOT are used) from five dif-ferent industrial application benchmark classes. We obtained the AIGs as described inthe following. hwmcc08-sat
204 satisfiable AIGs obtained from the Hardware Model Checking Com-petition 2008 problems . The original sequential circuits were unfolded using the aigtobmc tool (part of the AIGer package ) The step bound k = 45 was used forthe time frame expansion. smtqfbv-sat
61 satisfiable AIGs generated by using the Boolector SMT solver [8] tobit-blast QF BV (theory of bit-vectors) instances of the SMT Competition 2009 into AIGs. Based on our experience, given the large number of instances, 25 tries is enough to detect themain trends. The experiments described in Fig. 2 require more precision. Original instances available at http://fmv.jku.at/hwmcc08/ . Available at http://fmv.jku.at/aiger/ http://fmv.jku.at/boolector/ ss-sat-1.0
98 satisfiable AIGs from “formal verification of buggy variants of a dual-issue superscalar microprocessor” [23]. These circuits, originally in the ISCASformat, were converted to AIG using the ABC system [7]. vliw-sat-1.1
98 satisfiable AIGs from “formal verification of buggy variants of a VLIWmicroprocessor”, originating from the same place and converted to AIG in a similarfashion as sss-sat-1.0 instances. sat-race
Satisfiable AIGs filtered from a total of 200 instances used in the final roundof structural SAT track of the SAT Race 2008 and 2010 competitions. In order to be able carry out the experiments in practice, we picked a selection of atotal of 300 instances from these benchmark classes as follows. Based on the good per-formance reported in [6] for the
Depth-max heuristic, we filtered out trivial instancesfor
Depth-max (instances for which the median number of steps was < ). Fromthe remaining ones, in order to we picked those instances that we consider solved by Depth-max (i.e., instances for which the success rate for
Depth-max was ≥ %) .This resulted in the following distribution of instances: hwmcc08 – 95, smtqfbv – 46,sss-sat-1.0 – 61, vliw-sat-1.1 – 96, and sat-race – 2. Fig. 1 presents a “cactus” plot, i.e., the number of instances that can be solved within agiven time , summarizing the comparative performance of the 15 structure-based gateselection heuristics described in Sect. 4. The following conclusions can be drawn.First, we note that whenever a heuristic outperforms the baseline Rand heuristic, itsdual performs worse than
Rand , and vice versa. In fact, we see that in many cases thebetter the performance of a heuristic, the worse is the performance of its dual. This sug-gests that the properties proposed in Sect. 4 are meaningful in the context of CRS AT .One exception to the nice “symmetric” picture is the pair based on SCOAP combina-tional controllability CC , where the worse of the duals, CC-max , performs surprisinglyclose to the baseline
Rand – we will discuss this point later. An additional observationis that the depth-friendly heuristics
TFO-max , TFI-min , CC-min and
CO-max al-ways perform significantly better than their duals, and, furthermore, form most of thebest performing heuristics. This corroborates the hypothesis that there is an importantunderlying property correlated with the depth of gates.Second, we observe surprisingly good performance from the depth-agnostic
Flow-min . Recall that, intuitively, gates with high flow are those that have large influence onother gates in the circuit. Thus, on the surface, this result casts doubt on the role of the Available at Available at http://baldur.iti.uka.de/sat-race-2010/downloads.html This allowed us to perform these extensive experiments in practice within the given time frame.We hope to extend the experiments also to those instances unsolved by
Depth-max . The median CPU times were used for the plot. The median number of search steps would alsobe an appropriate measure for comparing the quality of search heuristics. However, the relativeperformance differences based on time and on number steps are very close in this case, andthe cactus plot using running times is easier to read. ig. 1.
A comparison of the performance of 15 gate-selection heuristics described in Sect. 4 as a cactus plot, i.e., the number of those instances that caneach solved within a given time limit. An instance is considered solved if a success rate over the 25 tries is ≥ . The CPU time of a solved instance isthe median CPU time for the instance over all runs (including the unsuccessful ones). C P U t i m e ( s e c ) number of solved instancesTFI-maxDepth-minFO-min TFO-minFlow-maxCO-min CC-maxRandFO-max CC-minCO-maxFlow-min TFO-maxDepth-maxTFI-min
100 1000 10000 100000 1e+06 1e+07 100 1000 10000 100000 1e+06 1e+07 TF I - m i n , nu m be r o f s ea r c h s t ep s Depth-max, number of search stepshwmcc08-satsmtqfbv-satsss-sat-1.0vliw-sat-1.1sat-race (a)
Depth-max vs TFI-min
100 1000 10000 100000 1e+06 1e+07 100 1000 10000 100000 1e+06 1e+07 TF I - m i n , nu m be r o f s ea r c h s t ep s Level-min, number of search stepshwmcc08-satsmtqfbv-satsss-sat-1.0vliw-sat-1.1sat-race (b)
Level-min vs TFI-minFig. 2.
Scatter plots that compare the performances of selected heuristics in terms of the mediannumber of steps, over 100 tries. Timed-out instances are plotted with the number of steps set to , on the vertical and horizontal lines. influential gates in the context of CRS AT . On the other hand, between the two dualsbased on the size of the fanout of gates, it is the FO-max that performs well, rather than
FO-min . A closer look at some of our instances resolves this apparent contradiction– the flow is not depth-agnostic, but, in fact, is negatively correlated with depth. Thereason for this is that most of our benchmark circuits have significantly more inputsthan outputs, and thus gates that are close to inputs tend to have small flow values. Atthe same time, we did not detect any interesting relationships between
Depth-max and
FO-min , most likely due to the fact that the latter is much more a local property thanthe former. This suggests that to further study the effects of “influence” of gates in thecontext of CRS AT , alternative measures are needed, e.g., ones that are based on graph-theoretic centrality measures. This conclusion is corroborated by the fact that, althoughthe depth-friendly heuristics capture high influence — gates with large depth often havelarge transitive fanout and thus have high influence through forward propagation — theresults show that TFO-max is not the best performing heuristic.Finally, we observe that the SCOAP-based heuristics
CC-min and
CO-max , as wellas the
TFO-max heuristic based on the size of the transitive fanout of gates, do not per-form as well as
Depth-max . However, in contrast, the heuristic that prefers gates with small transitive fanin , TFI-min , appears to perform noticeably better than
Depth-max .The scatter plot in Fig. 2(a) which compares the performance of these two heuristics interms of the number of search steps demonstrates that the size of the transitive fanin ofgates can provide a better guidance to CRS AT than the depth of the gate.Note that gates with small transitive fanin are very likely to be close to the inputs.Based on the theoretical analysis of CRS AT in [3] and [6] the performance of the algo-rithm should improve if it arrives to the input level frequently. Hence, to get insight intothe reasons of the good performance of TFI-min , we need to understand whether theheuristic is effective simply because it brings the algorithm faster to the input level, orwhether there is another mechanism at play. One way to investigate the answer to thisuestion is to compare the performance of
TFI-min with a heuristic that is based on ameasure that disregards the number of gates in the sub-circuit rooted at the gate, andtakes into account only the distance from the gate to the input level. Such a measure,well known in EDA literature, is called the level of a gate, and is defined as follows:
Level: level ( C, g ) , where the level of a gate g in C is level ( C, g ) = (cid:26) if g ∈ inputs ( C )1 + max { level ( C, g ′ ) | g ′ ∈ fanin ( C, g ) } otherwise.Thus, level ( C, g ) is simply the maximum distance from the gate g to an input gate,and so the depth-friendly heuristic based on level, Level-min , would control the searchsolely based on the distance to the inputs.The comparative performance of
TFI-min and
Level-min is presented in the scat-ter plot in Fig. 2(b). We observe that performances of the two heuristics are highlycorrelated. As such, this comparison does not give a definitive answer to the questionof which measure is more fundamental for CRS AT . To gain some insight, we can in-troduce heuristics that go for the input gates more aggressively than Level-min . Suchheuristics can, for instance, be based on the following measures:
LLevel: level ( C, g ) , where the “low” level of a gate g in C is llevel ( C, g ) = (cid:26) if g ∈ inputs ( C )1 + min { llevel ( C, g ′ ) | g ′ ∈ fanin ( C, g ) } otherwise. ALevel: alevel ( C, g ) , where the “average” level of a gate g in C is alevel ( C, g ) = (cid:26) if g ∈ inputs ( C )1 + P g ′ ∈ fanin ( C,g ) level ( C, g ′ ) / | fanin ( C, g ) | otherwise.Thus, the “low” level of g is the shortest distance from g to some input gate, whilethe “average” level of g is somewhere in between the level and the “low” level; thatis, we always have level ( C, g ) ≥ alevel ( C, g ) ≥ llevel ( C, g ) . As such, the LLevel-min heuristics will drive the search to the input gates extremely aggressively, while the
ALevel-min heuristic represents a middle ground between
Level-min and
LLevel-min .The cactus plot in Fig. 3 summarizes the comparative performance in terms of CPUtime of the three level-based heuristics described above and
TFI-min . We note that theperformance of level-based heuristics degrades as the heuristics attempt to drive thesearch towards the inputs more aggressively. This observation provides partial evidenceto the hypothesis that the size of transitive fanin of a gate, which provides an estimateof the amount of work needed to justify a sub-circuit rooted at the gate, is a morefundamental structural property in the context of CRS AT . However, in order to evaluatethis hypothesis properly, we need to discover classes of problems where the measures Level and
TFI are not correlated. Finally, due to the fact that on the instances in ourbenchmark set the two measures appear to be correlated, we note that since
Level is acheaper-to-compute measure, in practical applications one might want to consider using
Level-min , rather than
TFI-min , as a gate-selection heuristic. C P U t i m e ( s e c ) number of solved instancesLLevel-minALevel-minTFI-minLevel-min Fig. 3.
A comparison of the performance of
TFI-min with various level-based gate-selectionheuristics as a cactus plot, i.e. the number of those instances that can each solved within a giventime limit. An instance is considered solved if a success rate over the 25 tries is ≥ . TheCPU time of a solved instance is the median CPU time for the instance over all runs (includingthe unsuccessful ones). We presented results of experiments on the applicability of different circuit-level prop-erties as the basis of structure-based search (gate selection) heuristics for the state-of-the-art SLS method CRS AT for industrial-related Boolean satisfiability instances. Theresults can be seen as first steps towards understanding the role of structural informationin justification-based local search for SAT with limited Boolean propagation integratedinto the search. We identified a number of easy-to-compute structural properties whichappear suitable as the basis of heuristics for CRS AT , some of which can even outper-form the recently introduced depth-based variant of CRS AT . The promise of the result-ing heuristics was also corroborated by showing the dual properties result in extremelyweakly performing heuristics.The now presented results open up various interesting questions for further work onimproving structure-based SLS for SAT. First, the observation that somewhat differentlydefined structural properties result in good heuristics suggests to study different ways of combining the resulting heuristics for achieving even better performance. This includesthe question of what are the actual underlying properties to give good performance, andwhich the now studied easy-to-compute properties may be approximating. In additionto gate selection heuristics, we also aim to study different objective functions that arebased on structural properties of SAT instances. Finally, we note that the developmentof good structure-based search heuristics for the circuit-level is directly applicable forthe logical combinations of more high-level constraints (more generic CSPs), wherethe logical combinations can be viewed as circuits. This is one of the main researchdirections we are currently pursuing. Acknowledgements
We thank the anonymous referees for helpful comments. eferences
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