The performance and limitations of FPGA-based digital servos for atomic, molecular, and optical physics experiments
Shi Jing Yu, Emma Fajeau, Lin Qiao Liu, David J. Jones, Kirk W. Madison
TThe performance and limitations of FPGA-based digital servos for atomic, molecular,and optical physics experiments
Shi Jing Yu, Emma Fajeau, Lin Qiao Liu, David J. Jones,
1, 2, ∗ and Kirk W. Madison † Department of Physics & Astronomy, University of British Columbia, Vancouver, BC V6T 1Z1, Canada Quantum Matter Institute, University of British Columbia, Vancouver, BC V6T 1Z1, Canada (Dated: August 22, 2017)In this work we address the advantages, limitations, and technical subtleties of employing fieldprogrammable gate array (FPGA)-based digital servos for high-bandwidth feedback control of lasersin atomic, molecular, and optical (AMO) physics experiments. Specifically, we provide the resultsof benchmark performance tests in experimental setups including noise, bandwidth, and dynamicrange for two digital servos built with low and mid-range priced FPGA development platforms.The digital servo results are compared to results obtained from a commercially available state-of-the-art analog servo using the same plant for control (intensity stabilization). The digital servoshave feedback bandwidths of 2.5 MHz, limited by the total signal latency, and we demonstrateimprovements beyond the transfer function offered by the analog servo including a three pole filterand a two pole filter with phase compensation to suppress resonances. We also discuss limitationsof our FPGA-servo implementation and general considerations when designing and using digitalservos.
I. INTRODUCTION
Active stabilization of physical systems is common inexperimental science and ubiquitous in atomic, molec-ular, and optical (AMO) experiments. Consequently,feedback-based (i.e. closed loop) controllers are a funda-mental instrumentation element in every AMO physicslaboratory. Typically, stabilization is achieved us-ing proportional-integral-derivative (PID) feedback con-trollers realized with analog circuitry. However, signifi-cant progress in the speed and power of digital process-ing units has led to the possibility of replacing analogservos for feedback control with digital controllers. Theadvantages of a digital controller over an analog deviceare many and largely stem from the ability to easily andquickly reconfigure the controller or add complexity to itwith firmware or software changes. The characteristicsof a digital controller can be changed dynamically, andtherefore adaptive controllers can be easily implemented.In addition, the complexity of a digital controller is notlimited in a practical sense by fabrication time. Thisadaptability and potential for high complexity digitalcontrollers enables the realization of features includingout-of-lock detection, auto-locking [1, 2], multiple-inputand multiple-output transfer functions [1, 3–5], and self-analyzing features [1, 3] that would be very difficult andtime-consuming to realize with analog filters.Previous work on the implementation of digital con-trollers falls broadly under two categories - the use ofcomputers or microcontrollers for low speed control ap-plications and the use of digital signal processors imple-mented with field-programmable gate arrays (FPGA) toachieve high bandwidth feedback control. In particular, ∗ [email protected] † [email protected] microcontroller-based feedback systems are typically lim-ited to feedback bandwidths below about 100 kHz [6–8], whereas FPGA-based servos have been demonstratedwith feedback bandwidths as high as a few MHz [1, 9, 10].Among the FPGA-based servo designs, a few specializedall-digital or partially digital servo designs that forgo theuse of an analog-to-digital converter (ADC)/digital-to-analog converter (DAC) have demonstrated bandwidthsabove 5 MHz [4, 11]. In spite of considerable developmentin FPGA-based servos, what appears to be missing fromthe work published thus far is a detailed discussion of thelimitations of digital controllers in comparison with theiranalog counterparts and a side-by-side, quantitative com-parison of a digital servo with an analog controller tunedto implement the same transfer function.Ref. [1] presents an FPGA-based digital servo witha control bandwidth above 1 MHz capable of multiple-input, multiple-output control optimized for feedbackcontrol of lasers in AMO experiments. The authorsalso generously share their hardware and firmware de-sign as open source. They demonstrate auto-locking andtransfer function measurement features of their servoin two locking scenarios (frequency control of a laserand length control of a cavity). They note that limi-tations in servo performance can arise from finite preci-sion (i.e. fixed point) math, truncation of the filter co-efficients and data, and potential register overflow dueto high gain. They also provide a figure comparing theideal continuous time transfer function and the discretetime, integer math transfer function realized by the infi-nite impulse response (IIR) filters built into their digitalservo. Based on the similarity of the ideal and computedtransfer functions, they state that their choice of a 35 bit ×
35 bit signed integer multiplication is sufficient.The goal of this work is to examine some of the prac-tical limitations and subtleties of realizing a high speeddigital servo for AMO experiments and to provide a di-rect comparison of the lock performance of two different a r X i v : . [ phy s i c s . i n s - d e t ] A ug FPGA-based servos with a state-of-the-art commerciallyavailable analog servo prepared to realize the same trans-fer function. Two questions that we address are whatlevel of FPGA is actually needed for a well functioningservo, and what are the noise and bandwidth limitingelements in such a system? In addition, we discuss sev-eral subtle hardware and software issues that we foundimportant to consider in the design and implementationto achieve a high level of performance. In particular, wediscuss the relationship between the coefficient of resolu-tion and distortions in the implemented transfer functionand the impact of least-significant-bit (LSB) handling infixed point computations on over-sampling. We also dis-cuss how we achieved noise suppression in a closed loopcontrol scenario to a level below the analog noise floor ofthe ADC.This paper is organized as follows. Section II A dis-cusses aspects of our hardware design including com-ponent selection, latency characterization, and the roleof oversampling in the signal processing chain. Sec-tion II B discusses firmware and software implementationissues including an optimized IIR filter design, the role ofcomputational precision, our use of an embedded micro-processor, and our code description. Section III comparesthe baseline performance of two digital servos (based onthe Altera DE2 and DE3 development boards made byTerasic) with a commercial analog controller (VescentPhotonics D2-125 Laser Servo). We discuss the limita-tions of the servo bandwidth and noise floor and possibleimprovements to our design. Section IV presents a side-by-side performance comparison of the digital and ana-log controllers in a high-bandwidth control application,namely laser intensity stabilization using an acousto-optic modulator. We also demonstrate two improvementsin the FPGA servo with the use of proportional-integral-cubed (PI ) and proportional-double-integral (PII) withphase compensation transfer functions. II. DESIGN OF THE FPGA-BASED SERVO
A block diagram of our FPGA-based servo is shown inFig. 1 [12]. To control the servo, an external PC runsa MATLAB script that computes and uploads servo pa-rameters including infinite impulse response (IIR) filtercoefficients and servo gain and offset settings for the ana-log signal conditioning stages. In the following two sec-tions, we discuss the specific hardware configuration andFPGA firmware design.
A. Hardware Configuration
As illustrated in Fig. 1, each FPGA servo is composedof two voltage offset (VO) stages, two variable gain ampli-fier (VGA) stages, an ADC (including an ADC driver),a DAC and an FPGA. The VO stages and the VGAstages are components of the analog front- and back-end
FIG. 1. Layout of the FPGA-based digital servo. Each servoimplements two channels (the second channel is not shown).The analog region of the mixed-signal system is composedof VO (variable offset) circuits, VGAs (variable gain ampli-fiers) and an SDA (single-to-differential amplifier). Both theinput and output VOs and VGAs are controlled by the softcore microprocessor within the FPGA. The FPGA itself iscontrolled via RS-232 with a MATLAB GUI running on aPC. The latency of each stage, including the two differentFPGA platforms denoted DE2 and DE3, is indicated belowthe schematic. The circuit designs for the VO, VGA, andSDA can be found in Ref. [13]. of the FPGA servo and are responsible for tailoring theinput and the output of the servo signal to the operatingrange of the ADC and the DAC. Once the signal is con-verted into the digital domain by the ADC, the FPGA isresponsible for implementing the transfer function, elabo-rated in Section II B. Our design uses commercially avail-able FPGA development boards, the DE2 and DE3 byTerasic, and fast data acquisitions cards that are com-patible with these FPGA platforms (the Terasic AD/DAand ADA cards). In our first prototype, we implementedthe analog front- and back-end circuits using the AD829(for the VO) and the AD603 (for the VGA) on separateboards, and we modified the data acquisition cards to al-low DC coupling. Although some of the data presentedhere is taken with this first prototype system, we havesince developed a single daughter-card that implementsall the necessary elements and that is compatible withthe DE2, DE3, and the more recent FPGA platformsmade by Terasic [14].As discussed above, we benchmark the performance ofservos built with two different FPGAs, in part to explorethe requirements for developing an FPGA servo design.The DE3’s Stratix III FPGA is much more powerful thanthe DE2’s Cyclone II FPGA in terms of computationalresources, with 384 compared to 35 18 × / √ Hz. This noise and the noisefrom the VO stage originates, in part, from the noise ofthe slow-DACs (DAC7744 used in the prototype designand DAC8734 used in the custom daughter-card design)that are used to control the VOs and the VGAs. TheADC and the DAC also introduce noise into the signalchain above the 10 nV / √ Hz level. However, we find thatthe detrimental effect of the intrinsic output noise of theAD603 (VGA circuit) can be reduced by increasing theVGA gain, while the effect of the noise produced by theslow-DAC can be mitigated by scaling the voltage downwith a resistive divider at the output of the slow-DAC.Clearly, these two noise sources are not inherit to thedesign and result from our selection of integrated cir-cuit (IC)s used in this design.The noise and error introduced by the ADC/DAC is a result of introducing the digital domain. Quite remark-ably, due to over-sampling effects [15], the noise floor ofthe 14-bit ADC used in the DE2 servo is much lowerthan its quantization step (1
V / ≈ µV ). In prac-tice, we find the ADC noise floor to be limited by thenoise in the reference voltage: 136 nV / √ Hz at frequen-cies above 1 kHz and a -20 dB/decade slope (the pinknoise) at frequencies below 1 kHz. Noise levels in the100 nV / √ Hz range can become an obstacle to obtainingan overall noise floor in the 10 nV / √ Hz range. However,as we show in this work, it is possible for an FPGA servoto reach a noise floor lower than the analog noise floor ofthe ADC itself by carefully distributing the gain withinthe system. A discussion of this technique can be foundin Section III B.
B. FPGA Firmware
The high-speed signal processing tasks, including theservo logic, are handed in the FPGA fabric and the slowertasks (communication, slow ramp generation) are han-dled in the soft-core MCU. Detailed information on theNios II MCU used in our firmware can be be found inthe Hardware/Software Programmers Manual publishedby Altera [16, 17]. In this section, we discuss the servologic implementation, and we review the critical featuresof the IIR filter implementation for a closed-loop servoapplication.Figure 2 illustrates the implementation of an IIR fil-ter with 16-bit coefficients that have a 10 bit fractionalresolution. In this example, the IIR filter coefficients areimplemented in Q5.10 fixed-point (FP) number formatwhere 10 specifies the number of fractional bits, 5 is thenumber of integer bits, and one bit is used to encode thesign of the coefficient. Here, the IIR filter is implementedsimilarly to the direct form I (DFI) of an IIR filter (def-inition of DFI can be found in Ref. [18] or textbooks ondigital filters) and the FP coefficients, annotated in cap-ital letters, are related to the DFI definition of the IIRcoefficients (in lower case letters) as b n = B n / R and a n = − A n / R , where R denotes the fractional resolu-tion.In our design, we reduce computational complexity andincrease speed by implementing division and multiplica-tion by powers of 2 as shift operations and by avoidingthe need to negate past data in the feedback path (ourIIR filter implementation differs from the standard DFIby the sign of the coefficients in the feedback path).The bit width of each signal in the IIR implementationis annotated in grey in Fig. 2. The use of 24 bits for A ,as opposed to the 14 bits available at the IIR output, is ofparticular importance. Keeping these additional 10-bitsin the feedback path of the IIR is analogous to keeping3 more decimal places (in base 10) before the multiplica-tion operation. This dramatically reduces the roundingerror that would have otherwise occurred and is an es-sential feature to take advantage of over-sampling effectswithin the IIR filter [15]. It is important to note thatthis particular placement of the multiplication and divi-sion by 2 operations is critical to implement the IIRfilter with proper over-sampling. Σ B Σ B ÷ 2 ÷A
14 30 24 144031 41 42 32
FIG. 2. A schematic of a first-order IIR implementation (spe-cific to the DE2) with fixed point coefficients ( B , B and A ) with 10-bit fractional resolution is shown. The FPGAimplementation is constructed from simple operations includ-ing multiplication ( × ), addition ( (cid:80) ), and division ( ÷ ) by thepower of 2 implemented as a shift operation, saturation logic( ) and clock delays ( .). The placement of the multipli-cation and division by 2 operations is critical to correctlyimplement this IIR filter with proper over-sampling. The bitwidth of each data path is noted in grey, and we note thatthe 14 bit width of the input and output signals are limitedby the ADC and DAC conversion stages. The servo implementation on the DE3 platform is sim-ilar in layout to the IIR filter used in the DE2 servo,shown in Fig. 2. The main difference is the use of 32-bit coefficients and references to the digital signal pro-cessor (DSP) structures that are specific to the StratixIII FPGA. These added bits for the coefficients on theDE3 increase the frequency resolution for the placementof poles and zeros in the transfer function (see SectionIII C). The references to the DSP structure are necessaryto route data through the structures built in to the DSPthat make summation of multiple DSP outputs more ef-ficient. While these DSP features are convenient, theiruse makes the DE3 implementation only compatible withthe Stratix III FPGA, unlike the platform independentDE2 implementation.In terms of the computational delay in the servos, wenote that the delay through the IIR filter is small com-pared to the total conversion delay. In both the DE2and the DE3 IIR implementation, we are able to trimthe computational delay of each third-order IIR filter toone clock cycle where the clock frequencies are 50 MHz(DE3) and 125 MHz (DE2). This allows our design tocascade 2 to 3 third-order IIR filters while keeping thetotal signal latency of the servo under 200 ns.Here, we highlight two important observations regard-ing the behavior of the IIR filters that we implemented.Firstly, keeping additional LSBs in the IIR filter’s feed-back path is necessary to preserve the enhancement ob-tained by oversampling and to reach performance similarto that of the analog servo. This observation is corrobo-rated by numerical simulations, the details of which canbe found in Ref. [13].The second observation is that the saturation logic inour implementation leads to a peculiar problem when asingle IIR filter is used to realize multiple orders of inte- gration. In our IIR implementation, the saturation logicis a simple clamping logic placed at the IIR output (la-belled as the block in Fig. 2). This clamp prevents theIIR feedback signal from overflowing and the IIR outputregister from wrapping back to zero. This simple clamp-ing logic functions correctly for most use cases of the IIRfilter. However, for the specific scenario where a singleIIR filter implements a second- or higher-order integra-tion, the filter fails to correctly hold the output at therails when the input to the IIR filter is a constant non-zero offset. We believe that the source of the problemis that when the saturation logic activates, the effect isequivalent to adding an additional signal at the locationof the saturation logic. While a first-order integrationdoes not interact with this additional signal poorly, asecond-order (or higher order) integration of this signalresults in an additional ramp-like signal at the output ofthe IIR filter causing the problem described above. Asolution to this problem of realizing higher order inte-gration with this design is to cascade two or more IIRfilters.
III. BASELINE PERFORMANCE OF SERVOS
One of the main objectives of this work is to directlycompare the performance of the FPGA-based servos withan analog servo. In this section, we present baseline per-formance levels (of noise floor, bandwidth, and resolu-tion of transfer function) of each servo implementation.For this comparison, we use a commercially available,high performance analog servo (Vescent Photonics D2-125 Laser Servo).
A. Bandwidth
To characterize the speed of the servos, we measurethe frequency of the lowest feedback resonance producedby the servo when used in a closed loop setting withouta plant. This frequency defines what we refer to as theservo bandwidth ( f bw ) and is related to the total signallatency ( T ) by f bw (cid:39) / (2 T ). This bandwidth measureprovides an upper bound on the highest frequency thata servo can correct for and can be inferred from the to-tal signal latency through the servo system. In practice,the control bandwidth achievable is less than f bw and isdetermined by additional latencies or resonances intro-duced by the plant being controlled.The latency through an op-amp is determined by itsgain-bandwidth product (GBP) and the slew-rate of theop-amp. With the high GBP of presently available op-amps, it is not surprising for an analog servo, like the Ves-cent D2-125, to have a bandwidth higher than 10 MHz.Like the analog servo, the FPGA-based servo has analogsignal conditioning stages, but it also has two additionalsources of delay that further reduce the bandwidth, thesignal conversion delay in the ADC and the DAC and thecomputational delay in the FPGA.The bandwidths of the servos are measured with aStanford Research Systems SR780 Network Signal Ana-lyzer (from DC to 100 kHz) and with a Hewlett PackardHP 8753E Network Analyzer (100 kHz to 40 MHz) witheach servo configured for unity gain with only propor-tional feedback. For the digital servos, all IIR filtercomputations are still executed (3 cascaded IIR filtersall configured with unity gain) to properly quantify theeffect of the computational delay. The measured trans-fer functions for these proportional (P) controllers areshown in Fig. 3. These measurements verify the specified10 MHz bandwidth of the Vescent D2-125 and show thatthe FPGA servo has the 2.5 MHz bandwidth expectedfrom the 200 ns signal latency. This latency is mainlydue to the additional conversion delay introduced by theADC and the DAC and, to a smaller extent, the compu-tational delay in the FPGA as illustrated in Fig. 1. -180-135-90-450 P h ase ( d e g r ees ) Frequency (Hz) -50-40-30-20-100 M a gn i t ud e ( d B ) DE2 (digital) DE3 (digital) Analog DE2 (digital) DE3 (digital) Analog
FIG. 3. (color online) Transfer function of the servos whenconfigured as proportional controllers and measured withSR780 (up to 100 kHz) and HP8753E (100 kHz to 40 MHz).The only major difference is the bandwidth of the servos asdepicted by the intersection between the phase response ofeach servo and the 180 degree phase shift boundary (the blackdashed line).
As illustrated in Fig. 1, the signal latency through theFPGA servo is composed of several delay sources. Theconversion delay is 92(139) ns and accounts for 60(75)%of the total delay in the DE3(DE2) FPGA servo. Thecomputational delay takes up a smaller fraction as a re-sult of the speed optimization in designing the IIR logic,with the cascade of two third order IIR filters each cost-ing 64(47) ns for the DE3(DE2) servo and accounting for35(22) % of the total delay. The total delay through theanalog signal conditioning stages in this design is only30 ns (15% of the total) and is on the order of the totaldelay through an analog servo with similar op-amp tech-nology. The delay in signal conversion and, to a lesser extent, the computational delay are the primary culpritsin the additional delay in an FPGA servo.Does the additional delay in a digital servo limit itsapplication? Surely, because of the longer signal delay ofthe FPGA servo, the bandwidth of a control system em-ploying the FPGA servo cannot exceed 2.5 MHz. How-ever, because the bandwidth of a control system alsodepends on the signal latency through the rest of thesystem, the difference between the FPGA servo and theanalog servo may not be substantial when they are usedto control a plant that has a considerably longer latency.
B. Noise Floor
In this section, we discuss noise floor measurements ofeach servo. These measurements indicate the minimumsignal level that the servo can correct for. As a bench-mark for this comparison, the analog servo is specified tohave a noise floor of 10 nV / √ Hz by the manufacturer,and this value is confirmed by our measurements.To reveal the noise floor relevant to the servo perfor-mance in a control scenario, we set the transfer functionto PII with corner frequencies at 200 kHz and configureit in a closed loop by connecting the output directly tothe input. We refer to this as a self-locking configura-tion. The rationale for measuring the noise floor in thisself-locking (closed-loop) configuration rather than con-figuring the servo in open loop with unity gain is to revealthe input noise floor level of the servos. The input noiselevel is much more important than the output noise levelsince for any control system the noise at the output ofthe servo loop is suppressed across the servo bandwidthwhere the servo gain is large.The results of the noise floor comparison are shownin Fig. 4. The difference in the noise levels between theanalog servo and the FPGA servos for frequencies below30 kHz is less than 5 dB. We will refer to this low fre-quency region (frequencies below 30 kHz) as the suppres-sion band in the rest of the manuscript. It is remarkablethat the noise performance for the FPGA servos in thisself-locking configuration is below the noise floor of theADC itself. This was achieved by maximizing the inputsignal gain while keeping the total loop gain of the servofixed. For frequencies higher than 30 kHz, the FPGAservos have a higher noise level by at most 15 dB. Asdiscussed in Sec. II B, the FPGA servo noise level (in therange 50 to 100 nV / √ Hz) is larger than that of the ana-log servo ( ∼
10 nV / √ Hz) due to noise introduced bythe VGA, the ADC, and the DAC. This noise arises, inpart, from voltage noise on the reference voltage to theADC and voltage noise of the slow-DAC used to controlthe analog front-end settings.For closed-loop applications, the noise levels at differ-ent locations of the loop have a very different impact onthe output of the closed-loop system. Noise at the in-put of the servo is directly written onto the output ofthe system, while the noise at the output of the servo -160-155-150-145-140-135-130 N o i se ( d B V pp / √ H z ) Frequency (Hz)
Analog Servo DE3 Digital Servo DE2 Digital Servo
FIG. 4. (color online) The noise floor comparison of the ser-vos. The servos are configured as PII controllers in closed-loopwith the same total gain at high frequencies. The gain distri-bution of the analog servo was set according to the manufac-turer’s specifications; however, because the FPGA servo hasnoise sources on the input stage above 10 nV / √ Hz, the inputsignal gain is maximized before the ADC and then attenuatedeither in the FPGA logic or after the DAC accordingly to pro-duce the same total gain as the analog servo required for adirect comparison. This strategy yielded similar performanceto the analog servo at frequencies lower than 30 kHz. is suppressed due to the action of the servo itself. Toachieve the noise performance in the suppression bandshown in Fig. 4, we maximized the gain before the ADCand decreased the gain after the DAC accordingly (witha fixed attenuator) to keep the total loop gain constantand equal to the total loop gain of the analog servo. Wefound that decreasing the gain in the FPGA logic can alsobe used instead of reducing the gain after the DAC. Thislatter method has the advantage of maintaining the fullvoltage range of the servo output. This is often needed tocorrect a disturbance of a fixed amplitude. However, re-ducing the gain inside the servo logic must be done withcare, because the noise floor achievable by the logic andresolution of the transfer function can be affected in theprocess (see Ref. [13] for more details).In addition to the noise sources in the analog domain,the digital implementation of the servo has an effect onthe noise floor. As mentioned previously, correctly han-dling the LSBs in the IIR implementation is critical toachieving the best noise floor. In particular, we foundthat degradation of the signal quality in the digital logicimplementation often resulted from incorrect rounding ortruncation .
C. Transfer Function
In this section, we address the range of transfer func-tions that a servo can implement. Typically, analog ser-vos are designed with a discrete set of resistor-capacitor(RC) values to implement a discrete set of corner fre-quencies between 10 Hz and 1-2 MHz. The FPGA servoalso has a discrete distribution of poles and zeros dueto the underlying IIR implementation. In a first order IIR filter, the spacing between adjacent poles and zerosis roughly constant and equal to ∆ f = αf clk / R , whereR is the fractional resolution of the coefficient (its widthin bits), f clk is the clock frequency, and α is the scalingfactor which for this case is α = (2 π ) − [19]. For the im-plementation with the IIR coefficients in Q5.10 format(16-bit signed coefficients with a 10 bit fractional resolu-tion) and an f clk of 50 MHz, the frequency resolution is7.7 kHz. By contrast, for the implementation with theIIR coefficients in Q3.28 format (32-bit signed coefficientswith a 28 bit fractional resolution), the resolution is 48mHz. It is possible to improve the pole/zero resolutionof the IIR filter with 16-bit coefficients by slowing theclock, but we did not pursue this approach due to theadditional latency that would result.The frequency resolution of a high-order IIR filter ismore complex, since the frequency resolution of the ze-ros/poles affect one another [20]. However, it can beshown that a high-order IIR filter will, as a result ofthis correlation, have less precision in placing multiplepoles/zeros than placing a single pole/zero.Another effect that arises from the finite coefficientresolution is an inevitable distortion of the transfer func-tion. An example transfer function and its realization byan IIR filter with two different coefficient resolutions isshown in Fig. 5. Distortions in the magnitude and phaseare evident in both cases. Not only can distortions affectthe locking performance of the servo, but they can alsolead to dynamical instabilities due to the movement ofthe pole and zero locations from just inside to just out-side the stability region in the z-domain when the IIRcoefficients are rounded to the nearest hardware realiz-able value. This effect is described in various texts (seefor example section 9.4 of Ref. [21]) and continues to bea topic of study in control research [22].There are many strategies for reducing the effects offinite coefficient resolution on the accuracy of the imple-mented transfer function. Cascaded IIR filters and IIRfilters with lattice structures are two examples [21, 23].For complex transfer functions, including the PII with anintegrated lag-lead filter discussed in Section IV D, weuse a set of cascaded higher-order IIR filters in direct-form (DF) with 32-bit coefficients to implement the de-sired function with high fidelity and good resolution forfeature placement. Because the use of high resolutionIIR filters does not completely eliminate the possibilityof distortion, we use a MATLAB simulation to check fordiscrepancies between the desired transfer function andthe one implemented in the FPGA servo. IV. BENCHMARK TESTS
In this section, we discuss the use of the FPGA servosin an intensity stabilization apparatus (also referred toas a noise-eater) and compare their performance againstthe commercial analog servo (D2-125) characterized inSec. III. We also demonstrate the realization of transfer -20-1001020 M a gn i t ud e ( d B ) -90-45045 P h ase ( d e g r ees ) Frequency (Hz)
Ideal transfer function Implemented in Q5.10 format Implemented in Q3.28 format
FIG. 5. (color online) Numerical simulation of the trans-fer function that results from an IIR filter implementationof a PID controller with two different coefficient resolutions:Q5.10 (in blue) and Q3.28 (in red). In this particular case,the Q5.10 implementation has an unacceptable amount of dis-tortion at low frequencies and is dynamically unstable due tothe rounding of the IIR coefficients to the nearest hardwarerealizable value and the resulting movement of the locationof the pole/zero from just inside to just outside the stabilityregion in the z-domain. functions with the FPGA servo that are more complexthan that of the commercial analog servo, and we findsignificant performance improvement of the noise-eaterwith the use of PI and PII with phase compensationtransfer functions. A. Experimental Setup
As shown in Fig. 6, the intensity stabilization system isconstructed from an acoustic optical modulator (AOM)(IntraAction ATM series) and is controlled by a radio fre-quency (RF) source with a variable power realized witha variable attenuator (MACOM MAAVSS0006) nestedin the RF amplifier chain. The detection of the opticalintensity is done with a biased Si photodetector (Thor-labs DET10A) with a noise-equivalent power (NEP) of1 . × − W / √ Hz. The active components of the inten-sity stabilization system including the AOM, the variableattenuator, and the photo-detector all have fast rise/falltimes ( <
70 ns, 10 ns and 1 ns respectively). This leads toa relatively high open-loop bandwidth (3 MHz); however,the delay of the action of the AOM due to the propaga-tion time of the acoustic wave from the piezo-electric ele-ment to and across the laser beam inside the AOM addsa signal latency of 400 ns to the closed loop delay of theintensity stabilization system. This latency is the dom-inant delay, and therefore the closed-loop performancedifference of the system due to the bandwidth difference of the two types of servos is not substantial.
FIG. 6. Experimental set-up of the intensity stabilization(noise-eater) system. An arbitrary intensity noise is writ-ten on to the laser and then stabilized through a closed-loopformed by the servos used in this study, an AOM (acoustic-optical modulator) used as the modulator and an PD (photo-detector) used as a feedback detector. The out-of-loop de-tection (in dashed box) is used to verify that the intensitynoise is truly suppressed and is analyzed by a RFSA (radiofrequency spectrum analyzer).
A second AOM is used to inject additional intensitynoise into the laser light, and this is accomplished bymodulating the RF power using the voltage controlledattenuator and a voltage noise source produced by an ar-bitrary waveform generator (Stanford Research SystemsDS345). This set-up allows us to customize the spectrumof the noise and allows a more thorough study of thenoise suppression capability of the servos. In particular,we inject a wide-band ( >
10 MHz), white noise spectrumwith a magnitude large enough that the noise suppres-sion achieved by the full system system is far above andtherefore not limited by the shot-noise of the detectionsystem. This is done to insure that the comparisons weare making between servos is representative of their noisesuppression capability and not limited by shot-noise. Inaddition, while monitoring the output of the photodetec-tor in the servo loop (in-loop detection) provides someevidence of noise suppression, an additional photodetec-tor is used to perform an independent, out-of loop detec-tion of the intensity noise after the noise-eater. We notethat all of the data presented here is from an out-of-loopmeasurement except for the data on the performance ofthe PII with lag-lead phase compensation.
B. PII
The performance of the intensity stabilization systemis characterized by the relative intensity noise (RIN) ofthe output light and is shown in Fig. 7 with each servoconfigured as a PII controller. The width of the suppres-sion band is set by the highest corner frequency of the PIItransfer function. This corner frequency is set to 100 kHzfor the analog and 70 kHz for the FPGA servos. Highervalues worsen the loop resonances for each servo system.The analog servo has a small advantage in that it allows ahigher corner frequency due to its smaller signal latency.The second corner frequency is 10 kHz (7 kHz) and ischosen to be a decade below the higher corner frequencyfor the analog (FPGA) servo. The gain setting for eachservo is optimized for each measurement. -120-110-100-90-80 R I N ( d B c / H z ) Frequency (Hz) -120-100-80-60-40 I n t e g r a t e d N o i se ( d B c ) Analog Servo DE3 with PI DE2 with PI FIG. 7. (color online) Comparison of the relative intensitynoise spectra (thick lines referenced by the y-axis scale on theleft) achieved with the intensity stabilization system using thethree different servos controlling the same plant. The thinlines represent the integrated noise (referenced by the y-axisscale on the right) from 20 Hz up to a given frequency.
Figure 7 shows that the RIN of the stabilized laser sys-tems are similar both inside and outside the suppressionband. This result is different from the noise floor mea-surement of the servo in Section III B, where the servoshave similar noise floors inside and different noise floorsoutside the suppression band. In this system, the noiseoutside of the suppression band is dominated by the noiseinjected by the AOM. Because the PII controller is in-capable of suppressing this out-of-band noise, the noisefloor difference between the FPGA servo and the ana-log servo does not cause a visible difference. In addition,unlike the self locking data, here the loop resonance fre-quencies are almost the same (700 kHz and 1 MHz). Thisis due to the dominant loop delay introduced by the ac-tion of the AOM (about 400 ns).
C. PI As a natural extension of the PII servo, a PI fil-ter is implemented for the intensity stabilization system.This is accomplished by cascading three IIR filters in theFPGA servo, all configured as integrators. The perfor-mance of a PII filter realized by the analog servo anda PI filter realized by the FPGA-based servo is com-pared in Fig. 8. The PI filter widens the suppressionband without increasing the oscillation amplitude at theFPGA-based servo loop delay resonance. This is an ex-ample of a filter that cannot be implemented in the ana-log servo without additional hardware, while it can beimplemented in the FPGA servo with ease. -120-110-100-90-80 R I N ( d B c / H z ) Frequency (Hz) -120-100-80-60-40 I n t e g r a t e d N o i se ( d B c ) Analog Servo DE3 with PI FIG. 8. (color online) Relative intensity noise spectra (thicklines referenced by the y-axis scale on the left) achieved withthe intensity stabilization system using the analog servo andthe FPGA-based servo with different transfer functions. Thethin lines represent the integrated noise (referenced by they-axis scale on the right) from 20 Hz up to a given frequency.The analog servo realizes a PI with the two poles located at10 kHz and 100 kHz, whereas the digital servo is configuredto realize a PI with three poles located at 10 kHz, 100 kHz,and 100 kHz. We note that while this significantly increasesthe suppression band, this comes at the cost of additionalamplitude at 70 kHz. D. PII+LL
The lag-lead filter is another example of a filter thatcannot be easily implemented in an analog servo. Unlikethe PI filter, that can be constructed by chaining to-gether multiple analog servos, the lag-lead filter is rarelyimplemented in a general-purpose analog servo due tothe additional impedance networks that are necessary tomake all the poles and zeros tunable.The lag-lead filter is effectively a notch filter com-posed of two poles and two zeros. This is not to beconfused with the lead-lag filter, although both can beused as phase compensators in different applications. Asummary of the two types of phase-compensators canbe found in various sections of Chapter 9 of Ref. [24].Here, the lag-lead filter is used to suppress the loop res-onance of the FPGA-based servo at 700 kHz. The effectof this notch filter on the loop resonance is demonstratedin Fig. 9. Because the lag-lead filter reduces the gainlocally at the loop resonance, the amplitude of the looposcillation is reduced.We note that the PII + lag-lead transfer function con-tains a total of 4 poles and 4 zeros and is very susceptibleto distortions of the transfer function when the IIR coeffi-cients are rounded. This issue is addressed by distribut-ing the low frequency zeros in the PII in separate IIRfilters that are cascaded and by checking with numer-ical simulations for discrepancies between the intendedtransfer function and the implemented one. -120-110-100-90 R I N ( d B c / H z ) Frequency (Hz) -120-100-80-60-40 I n t e g r a t e d N o i se ( d B c ) DE3 with PI and lead-lagDE3 with PI FIG. 9. (color online) Relative intensity noise spectra (thicklines referenced by the y-axis scale on the left) achieved withthe intensity stabilization system using the FPGA-based servoconfigured with two different transfer functions : a PII anda PII with lag-lead. The thin lines represent the integratednoise (referenced by the y-axis scale on the right) from 20 Hzup to a given frequency. The lag-lead is a notch filter witha center frequency of 700 kHz. The lag-lead filter suppressesoscillations at the loop resonance of the servo system.
V. CONCLUSIONS
In this work, we present two FPGA servo designs usingthe Altera DE2 and DE3 development boards made byTerasic that achieve a total signal latency of 200 ns. Asdiscussed, the DE3’s Stratix III FPGA is a factor of tenmore powerful (and more expensive) than the DE2’s Cy-clone II FPGA in terms of computational resources; how-ever, for the purposes of implementing the digital servosexplored in this work, the resources on the low-end DE2FPGA were completely sufficient. We provide bench-mark performance comparisons of noise, bandwidth, anddynamic range of these FPGA servos with a commer-cial analog servo. We also provide a direct comparisonof the lock performance of the FPGA-based servos withthe analog servo using the same plant for intensity stabi-lization of a laser beam. For this control application, wealso demonstrate the realization of more complex transferfunctions including a PI and a PII with lag-lead phasecompensation to suppress the loop resonance of the in-tensity noise system. We also discuss the role of gaindistribution in the servo and how maximizing the inputgain while keeping the total loop gain constant is a viabletechnique for achieving noise suppression to a level belowthe analog noise floor of the ADC.We also discuss several subtle hardware and softwareissues that we found important to consider in the de-sign and implementation to achieve a high level of per-formance with the FPGA servo. In particular, we discussthe primary sources of noise and latency in our designand how these could be improved, and we discuss severalsubtle aspects of floating-point arithmetic and how theyaffect the behavior of IIR filters. We discuss transferfunction distortion and frequency quantization of polesand zeros arising from FP representation of the IIR fil- ter coefficients as well as the the role of LSB handling inFP computations and its impact on over-sampling as itpertains to signal processing.Some observations made in this work that we wish toreiterate here are as follows. First, the ADC is the largestcontributor of noise in our servo design. Its noise floorin the low 100 nV / √ Hz range is quite large compared tothat of standard op-amps used in analog servos (typicallyin the low 10 nV / √ Hz range). Due to over-sampling, aneffect that requires a small amount of white noise per-turbing the input of the ADC, this noise floor is wellbelow (here, on the order of 500 times smaller than) thequantization step of the ADC. While the noise floor ofADC devices does decrease as their resolution increases,this comes at the cost of additional delay and thus aloss of bandwidth of the servo. As a result, we find thatthe optimal performance is achieved by maximizing theinput gain while keeping the total loop gain constant.Second, we find that because over-sampling also plays animportant role in the FP math of the IIR filter itself, theservo logic itself can lead to degradation of the signal ifhandled incorrectly. Third, we wish to reiterate that thecomplexity of the transfer function that a digital servocan realize is limited by the fractional resolution of itsIIR coefficients. When the coefficients do not have suf-ficient resolution, a significant discrepancy between theimplemented transfer function and the desired transferfunction may result, including the exact placement ofpoles and zeros.Finally, we note that the bandwidth limitations of ourFPGA servo are primarily limited by the conversion de-lays and thus by available ADC technology. However,this limitation is not relevant for applications requiring acontrol bandwidth of ≤ ACKNOWLEDGMENTS
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