Transistor Switches using Active Piezoelectric Gate Barriers
aa r X i v : . [ c ond - m a t . m e s - h a ll ] M a y Transistor Switches using Active Piezoelectric GateBarriers
Raj K. Jana, Arvind Ajoy, Gregory Snider, and Debdeep Jena
Abstract —This work explores the consequences of introducinga piezoelectric gate barrier in a normal field-effect transistor.Because of the positive feedback of strain and piezoelectriccharge, internal charge amplification occurs in such an elec-tromechanical capacitor resulting in a negative capacitance. Thefirst consequence of this amplification is a boost in the on-current of the transistor. As a second consequence, employingthe Lagrangian method, we find that by using the negativecapacitance of a highly compliant piezoelectric barrier, one canpotentially reduce the subthreshold slope of a transistor below theroom temperature Boltzmann limit of 60 mV/decade. However,this may come at the cost of hysteretic behavior in the transfercharacteristics.
Index Terms —Electrostriction, Electromechanical capacitor,Piezoelectric barrier, Negative capacitance, PiezoFET, Subthresh-old slope
I. I
NTRODUCTION S CALING of the size of field-effect transistors (FETs) hasimproved their performance and integration densities inintegrated circuits for over two decades. Most conventionaltransistors make use of a passive insulating barrier layerbetween the gate metal and the semiconductor channel tomodulate the density of conduction channel electrons or holes.Because the intrinsic properties of a passive gate barrier donot change with the applied voltage, they impose certainfundamental limitations on the resulting device performance.One such limitation is the subthreshold slope, i.e. the gatevoltage required to change the drain current by an order ofmagnitude [1], [2], given by SS = m ×
60 mV/decade atroom temperature [3], [4]. Here, m = 1 + C sc /C ins is the‘body factor’, C sc is the semiconductor channel capacitance,and C ins is the gate insulator capacitance. In a traditional FETswitch with a passive gate dielectric such as SiO , C ins > and thus m > , which leads to SS > mV/decade [4]. Thisresult, combined with circuit requirements for the on current I on and the on/off ratio I on /I off establish a minimum supplyvoltage V dd , which does not scale in direct proportion withfeature size [1], [2], [5]. Scaling of V dd has hit a roadblock,giving rise to heat generation associated with the large powerdissipation density in ICs [1], [2], [6], [5], since the dissipatedpower is proportional to the square of the voltage, P diss ∝ V dd [2], [7]. Many ideas based on alternate transport mechanismsin the semiconductor channel, such as interband tunneling, orimpact ionization are being explored to lower V dd .An interesting alternative is to replace the passive gatebarrier with an active one. A first proposal of an active R. K. Jana, A. Ajoy, G. Snider, and D. Jena are with the ElectricalEngineering Department, University of Notre Dame, Notre Dame, IN, 46556USA e-mail: [email protected]; [email protected]; [email protected]; [email protected]. ferroelectric insulator [3] predicts internal voltage gain : thevoltage across the gate insulator layer is larger than the appliedexternal gate voltage. The origin of internal voltage gain isthe collective alignment of the microscopic electric dipolesin the ferroelectric layer in response to the external electricfield produced by the gate voltage. The alignment of dipolesgenerates a voltage of its own, thus amplifying the voltagethat makes it to the semiconductor channel. Under appropriatebias conditions [3], the insulator capacitance provided by theferroelectric is mathematically negative ( C ins < ), causing m = 1 + C sc /C ins < and SS < mV/decade. Suchan active-gate FET then will require a lower gate voltage tocreate the same charge as a conventional FET with passivegate dielectrics [3], thereby facilitating device scaling.In this paper, we explore the device consequences of us-ing a piezoelectric insulator as the active gate barrier in atransistor instead of the ferroelectric barrier. Piezoelectric gatebarriers are at the heart of commercially available III-nitrideheterostructure transistors [8], [9]. We first consider an activecompliant piezoelectric layer as the insulator in a parallel platecapacitor. We find that this simple electromechanical capacitorsystem exhibits a remarkably rich range of behavior. We showthat negative capacitance emerges as a natural response toapplied voltage. In this regime of negative capacitance, weshow that we obtain a higher charge than in a correspondingcapacitor with a passive dielectric. Non-trivial capacitance-voltage behavior in such capacitors have also been reportedexperimentally [10], [11]. Next, we port the parallel-plateelectromechanical capacitor to the gate capacitor of a FET.We show how this piezoelectric gate stack enables a higheron-current than in a transistor with a passive dielectric dueto internal charge amplification. Finally, building upon ourearlier proposals [12], [13], [14], we discuss the possibility ofusing the negative capacitance regime of a highly compliantpiezoelectric barrier to obtain sub- mV/decade switching ina transistor.II. E LECTROMECHANICAL CAPACITOR
We begin by discussing the piezoelectric parallel-plate ca-pacitor. Consider the parallel plate capacitor of area A shownin Fig. 1 (a). The equilibrium thickness t of the piezoelectricinsulator layer sandwiched between the metal plates changes to t = t − δ when a voltage V is applied on the plates, as shownin Fig. 1 (b). The strain is defined as s = δ/t . The equal andopposite sheet charges σ m that develop on the metal platesset up an attractive force between them, which strains theinsulator. This effect, called electrostriction, is the electric-field MetalPiezoelectric V= t Metal MetalPiezoelectric V> t - δ MetalStrain = s = δ/t σ m -σ m -σ s σ s ρ(z) (a) (b) Fig. 1. (a) Schematic cross section of a parallel-plate electromechanicalcapacitor with piezoelectric barrier layer of thickness t at V = t − δ when voltage V is applied. Sheet chargedistribution ρ ( z ) with ± σ m on the metal plates and surface charges ± σ s onthe piezoelectric. induced reduction of the thickness of a material; it occurs in all insulators, whether or not the layer is piezoelectric. Howeverif the insulator is piezoelectric, the strain amplifies the surfacecharge of the insulator. This mechanism sets up a positivefeedback between the thickness and the electric field, andis responsible for the appearance of negative capacitance. Tofind the capacitance in the presence of such electromechanicalcoupling, one must first find the net metal charge σ m as afunction of the external (battery) voltage, and then take itsderivative. This requires us to identify the surface charges σ s that develop at the surface of the insulator. The resultingelectric field profile is constant, equal to E = V /t , and thevoltage drops linearly across the insulator.Maxwell’s boundary conditions across the metal-insulatorinterface requires the normal components of the displacementvector to obey D d − D m = σ m . D d is the displacementfield in the dielectric related to the surface charges σ s by D d = ǫ E + σ s , where σ s = ( ǫ d − ǫ ) E + e s + σ sp or D d = ǫ d E + e s + σ sp . Here ǫ d = ǫ (1 + χ d ) is the netdielectric constant of the piezoelectric layer, and χ d is itselectric susceptibility. The electric field is E = V /t , where t = t (1 − s ) is the thickness of the strained insulator layer.We explicitly allow for both piezoelectric and spontaneous po-larization for an active dielectric material. The strain-inducedpiezoelectric contribution to the charge (to linear order) is e s , where e is the piezoelectric coefficient in units of C/m and s = δ/t is the strain along the field. The charge due tospontaneous polarization is σ sp , also in units of C/m . Insidethe metal, D m = 0 . Therefore, we obtain the relation σ m = ǫ d Vt (1 − s ) + e s + σ sp . (1)This relation illustrates how the strain s explicitly entersthe electrostatic relation between the metal charge and thevoltage across the capacitor. If one neglects the spontaneouspolarization ( σ sp → ), piezoelectric effect ( e → ) andstrain ( s → ), we get σ m = C V , (with C = ǫ d /t ),the standard textbook formula of a parallel plate capacitor.However, we note that one can turn off the spontaneous andpiezoelectric polarization by choice of material, and yet thefactor (1 − s ) in the denominator will persist: this is theelectrostriction term.The mechanical pressure P experienced by the insulatoris the electrical force F per unit area A . It is thus related to the metal charge [15], [16] via P = F/A = σ m /ǫ d . Tolinear order, the pressure depends on the strain via the stiffnesscoefficient P = C s , where C is in units of N/m , orPascals. Thus, we obtain the strain as a function of the metalcharge: s = σ m /ǫ d C . Substituting in Eq. 1 and rearranging,we have the desired relation between the metal charge inresponse to an applied voltage: C V = σ m − σ sp + ( σ sp − e ) ǫ d C σ m − ǫ d C σ m + e ( ǫ d C ) σ m . (2)The right hand side is a fourth order polynomial in σ m ,and captures the electromechanical coupling physics. Let usexplore its consequences. The sheet charge on the metal n m = σ m /q from Eq. 2 is plotted as a function of the appliedvoltage V in Fig. 2 for different sets of material parameters.For example, e = 3 . C/m , ǫ d = 15 ǫ correspond to thepiezoelectric material Sc x Al − x N [17], [18]. The value of C is allowed to vary arbitrarily in order to investigate the rangeof behavior of the piezoelectric capacitor. We also assume σ sp = 0 . A non-zero value of σ sp merely causes a horizontalshift of the σ m − V curve (see Supporting document). Thephysics of the piezoelectric capacitor with σ sp = 0 becomesapparent by factoring Eq. 2 into V = qC ( n m ) (cid:18) − n m n η (cid:19) (cid:18) n m n η (cid:19) (cid:18) − n m n π (cid:19) , (3)where qn m = σ m , qn π = ǫ d C /e , and qn η = √ ǫ d C .Setting V = 0 in Eq. 3, we obtain four real roots n m = 0 , + n η , − n η and + n π . For a rigid ( C → ∞ ), non-piezoelectric( e = 0 ) insulator, n η , n π → ∞ , whereupon we recover σ m = qn m = C V , and the metal charge is a linear functionof voltage as shown in the green line in Fig. 2(a).On the other hand, for a compliant non-piezoelectric in-sulator, C > , and Eq. 3 reduces to a cubic equationwith roots , ± n η at V = 0 . This is in fact a prototypicaldescription of a nano-electromechanical switch [19]. The twoadditional roots ± n η make the dependence of σ m on V nonlinear with two additional zero crossings. Multiple zerocrossings of the qn m − V curve mathematically guaranteesthat there must be regions of negative slope d ( qn m ) /dV < .This is shown in red in the flipped S-shaped curve of Fig.2(a), where C = 1 GPa is assumed. In these regions, theelectromechanical capacitor has a negative capacitance.However, the negative capacitance corresponds to very highvalues of charge density( > cm − ) and strain s ( > C > and e > . Notice that n η is independent of e . The root n π depends on e and its location determinesthe shape of the qn m − V curve. If e > √ ǫ d C , then < n π < n η and negative capacitance appears in the twocharge segments [ n = − n η , n ] and [ n , n ] shown in redin Fig. 2. It is important to realize that piezoelectricity lowersboth the charge density ( ∼ cm − ) [inset of Fig. 2(a)]and strain < . [Fig. 3(b)] at which negative capacitance −4−3−2−101234 x 10 −12 −10 −8 −6 −4 −2 0 2 4 6 −8 −6 −4 −2 0 2 4 −4−3−2−101234 x 10 C = G P a є d = є σ s p = C / m t = . n m Applied voltage, V (V) S h ee t c h a r g e d e n s i t y , n m ( / c m ) Not allowed(strain > 1)Dielectric qn m = C V Not allowed(strain > 1) n =n η n n n V (V) −0.2 −0.1 0−2024 x 10 Applied voltage, V (V)Piezoelectric barrier C = 0.01 GPa e = 3.1 C/m є d = 15 є σ sp = 0 C/m t = 0.5 nm d(qn s ) /dV > 0d(qn s )/dV < 0 (b)(a) n π e = 3.1 C/m e = 0 C/m −1−0.5 0 0.5 1−4−2024 x 10 V (mV) n n n n n Not allowed(strain > 1)Not allowed(strain > 1) n π n n n = - n η Fig. 2. a) Charge-voltage ( qn m − V ) characteristic of the electromechanical capacitor. Various charge states such as the positive capacitance segments [ n , n ] , [ n , n ] where the slopes C PE = d ( qn m ) /dV > are positive, and negative capacitance segments [ n , n ] , [ n , n ] where C PE = d ( qn m ) /dV < areshown, b) The characteristics of a piezoelectric capacitor with a lower stiffness and more compliant barrier with C = ∼ cm − , as shown in the inset. S t r a i n , s Applied voltage, V (V) t ( - s ) ( n m ) Applied voltage, V (V) −2 −1 0 100.20.40.60.81 C = 1 GPa e = 0 C/m є d = 15 є σ sp = 0 C/m t = 0.5 nm −4 −2 0 200.20.40.60.81 Piezoelectric C = 1 GPa e = 3.1 C/m є d = 15 є σ sp = 0 C/m t = 0.5 nm(b)(a) Fig. 3. Strain as a function of voltage in a) a non-piezoelectric insulatorlayer with C = e = , t = C = e = . Strain s < is physically accessible in solid state, where the remaining layer thickness, t (1 − s ) >
0. Red (black) represents strain corresponding to the negative(positive) capacitance charge states. appears, compared to electrostriction alone. For vanishinglysmall voltages around zero, the piezoelectric capacitor behavesexactly like a parallel plate capacitor - a straight line. Butthe additional benefit of the above coupling is the increasedcharge density compared to a passive dielectric due to thepiezoelectric amplification - this effect will boost the on-state current in a transistor. From Eq. 3, the piezoelectricamplification is n m − C Vq ≈ n m n π + ... to leading order. Finally,if we use a highly compliant piezoelectric, for example with C = 0 . GPa, negative capacitance can be accessed at verylow charge density ∼ cm − , as indicated in Fig. 2(b).These highly compliant piezoelectrics can potentially enablethe design of transistors with steep sub-threshold behavior,but require new materials as will be described later. We alsoremark here that Pauli’s exclusion principle of solid matterand quantum compressibility restricts s < . Therefore forpiezoelectric insulators, the metal charge will be restricted to − n η < n m < + n η . It may be possible to go beyond theserestrictions ( s > , shown as dashed lines in Fig. 2) in gaseousplasmas where charged ion plate ‘electrodes’ can pass througheach other. But we do not pursue that line of analysis here,by restricting the discussion to solid metals and dielectrics.III. T RANSISTOR WITH A P IEZOELECTRIC B ARRIER
PiezoelectricSemiconductorS D E C E Fs G V gs V ds qV gs ’ qφ B qV ΔE C I d C PE C sc t L ψ s V gs ’ V gs ’ R d R s Metal
Fig. 4. Schematic cross section of a transistor (“piezoFET”) with apiezoelectric gate barrier, semiconductor channel such as Si, GaN or 2Dmaterial, MoS , and source and drain ohmic contacts. The gate capacitancecircuit is a series combination of the piezoelectric capacitance C PE andthe semiconductor capacitance C sc . Here intrinsic gate voltage V ′ gs = V gs − I d Rs , and intrinsic drain voltage V ′ ds = V ds − I d ( R s + R d ) , where R s and R d are the source and drain contact resistances. The energy band diagramis shown for the metal-piezoelectric-semiconductor stack of the transistor. ψ s = V ′ gs − V = ( E F s − E C ) /q is the surface potential. We now explore how the presence of the piezoelectriccapacitor in the gate of a transistor with a semiconductor chan-nel changes the traditional characteristics. The semiconductorchannel could be formed of a gapped 2-dimensional crystalsuch as MoS , or a 3-D crystal semiconductor such as Si orGaN. The semiconductor is characterized by the valley degen-eracy g v of the conduction (or valence) band. We assume theenergy dispersion of each valley to be the same, characterizedby an effective mass m ⋆ and spin degeneracy g s = 2 . Carriertransport in the semiconductor channel is assumed to be 2-dimensional - which holds both for monolayer 2D crystalsand in field-effect transistors made of 3D semiconductors, Intrinsic Gate voltage, V gs’ (V) G a t e c a p a c i t a n c e , C g ( μ F / c m ) n s ( c m - ) V (V) D r a i n c u rr e n t , I d ( m A / μ m ) Gate voltage, V gs (V)BallisticGaN channel300K V ds = C = 1GPa e = 3.1 C/m є d = 15 є σ sp = 0 C/m t = 0.5 nm60 mV/decDielectric I on ~ 7.7% (c) −0.8 −0.6 −0.4 −0.2 0 0.2 0.4−2−1012345 x 10 Piezoelectric C = 1 GPa e = 3.1 C/m є d = 15 є σ sp = 0 C/m V gs’ = V gs’ = - V gs’ = a a −0.3 −0.2 −0.1 0 0.1 0.2 0.30510152025 Piezoelectric C = 1 GPa e = 3.1 C/m є d = 15 є σ sp = 0 C/m t = 0.5 nmDielectric GaN channel300KPiezoelectricS.C channel C PE C sc } C g Gate metal C C sc / ( C +C sc )(a) V gs’ C PE C sc / ( C PE +C sc ) Fig. 5. a) Gate capacitance C g versus V ′ gs for transistors with piezoelectric (solid line) and dielectric (dashed line) insulators, b) Graphical load line analysisto obtain sheet carrier density n s for different V ′ gs . Blue curves show the semiconductor charge for different V ′ gs , green shows the metal charge in the caseof a passive dielectric, whereas red(black) shows the metal charge in the negative(positive) capacitance regimes of the piezoelectric capacitor. Intersections a and a of the above characteristics define the operating points of the system, c) Transfer curve depicts the drain current I d versus V gs at drain voltage V ds = where transport occurs in a quasi-2D electron/holes gas. Theoccupation of multiple 2D subbands can then be treated asindividual 2D channels - we consider a single subband model.The semiconductor channel of length L and width W is assumed to be connected to very low-resistance ohmiccontacts at the source and drain, as shown in Fig. 4. Theenergy-band diagram in Fig. 4 shows the potential barriercontrolled by the voltage on the gate metal. Electrical chargeneutrality requires σ m = qn s , where n s is the mobilecarrier sheet density at the ‘top-of-the-barrier’ in the energyband diagram along the length of the channel. The energyband diagram from the metal to the semiconductor requires qφ B + qV − ∆ E c + ( E F s − E c ) = qV ′ gs . By suitable choiceof materials, we assume that qφ B = ∆ E c ; if this is not thecase, the difference can be absorbed in a shift of thresholdvoltage. When no drain voltage is applied, carriers in thesemiconductor are in thermal equilibrium with the source anddrain reservoirs, which for a parabolic 2D bandstructure means qn s = C sc V th ln (1 + exp[( E F s − E c ) /kT ]) , or E F s − E c = kT ln (exp[ qn s /C sc V th ] − , where C sc = q g s g v m ⋆ / π ~ is the density of states semiconductor capacitance, and thethermal voltage V th = kT /q . From the energy band diagramin Fig. 4, the relation between the applied gate voltage V ′ gs and the voltage drop V across the piezoelectric insulator is qV ′ gs = qV + ( E F s − E C ) . Here, ( E F s − E c ) /q = ( V ′ gs − V ) = ψ s is the surface potential. Using the carrier densityexpression and Eq. 2, the gate-induced charge qn s in thesemiconductor channel is self-consistently calculated. Finally,using this new dependence of charge on the voltages and thepiezoelectric coefficients, the current-voltage characteristics ofthe piezoFET are obtained from the ballistic transport model[21] incorporating the quantum contact resistances of 0.026k Ω . µ m [22] at the source and drain ends.Fig. 5 shows the gate capacitance C g = d ( qn s ) /dV ′ gs , anddevice characteristics ( I − V ) of a ballistic piezoFET with a GaN channel ( m ⋆ = m , g v = C g is obtained in the piezoFET (solid line),as compared to a FET with a passive gate (dashed line). Thehigher C g is due to the negative capacitance resulting frompiezoelectric charge amplification: C P E C sc / ( C P E + C sc ) >C C sc / ( C + C sc ) when C P E < . Fig. 5(b) depicts the solu-tion of the piezoelectric and semiconductor charge equationsgraphically, following the load-line approach (see [24]). Theblue lines depict charge in the semiconductor channel, and thegreen, black, and red lines depict the charge drawn into themetal from the battery. They must be equal to maintain globalcharge neutrality, meaning the locus of intersections are theoperating points of the device. The green line is the chargeon the metal for a traditional passive gate dielectric, and thered/black lines for a piezoelectric gate. When the transistor ison ( V ′ gs ∼ + 0.3 V), an increase in the charge at point a inFig. 5(b) is seen for the piezoelectric compared to point a for a passive dielectric. This increased charge boosts the on-current as depicted in Fig. 5(c), consequently improving the I on /I off ratio. This sort of piezoelectric amplification is aninteresting method to boost the on-current in any transistor.Since much of the high-performance characteristics such asgain and cutoff frequencies depend on I on , correspondingboosts can be expected in these parameters. This may bespecially useful for boosting the current in FETs made ofrelatively low mobility channel materials. Note however inFig. 5(c) that this device still has a SS of mV/decade. Thisis because the negative capacitance regime is only accessiblefor charge densities ≥ . × cm − : at this high levelof charge, the transistor is in its on-state, rather than in thesub-threshold regime.Because the charge-voltage characteristic of the piezoelec-tric capacitor is highly non-linear, it can have multiple inter-sections with the semiconductor load line. Ref. [25] developsa systematic procedure to understand such non-linear systems n s ( c m - ) n s (cm -2 ) E n e r g y , G ( J / m ) V (V) −6 −4 −2 0 2 4−3−2−10123 x 10 Piezoelectric C = 1 GPa e = 3.1 C/m є d = 15 є σ sp = 0 C/m V gs’ = V gs’ = V gs’ = - V gs’ = −0.4−0.3−0.2−0.100.10.20.30.4 (b) V gs’ = V gs’ = V gs’ = V gs’ = - −4.8−4.7−4.6 x 10 −3 n s (cm -2 ) V gs’ = Fig. 6. a) Load line analysis showing multiple intersections of the piezoelectric and semiconductor characteristics for different V ′ gs , b) Free-energy landscapeof the piezoelectric-semiconductor stack at various V ′ gs . Blue and black dots show stable operating points. Gate voltage, V gs (V) D r a i n c u rr e n t , I d ( m A / μ m ) n s ( c m - ) −3 −2 −1 000.20.40.60.811.21.4 BallisticGaN 300K V ds = V (V) D r a i n c u rr e n t , I d ( m A / μ m ) −0.2 −0.15 −0.1 −0.05 0 0.05 0.110 −3 −2 −1 Compliant piezoelectric C = 0.01 GPa e = 3.1 C/m є d = 15 є σ sp = 0 C/m t = 0.5 nm I d (mA/μm) SS ( m V / d e c a d e ) −3 −2 −1 V ds = V gs (V)< 60 mV/dec60 mV/decGaN channel300K(a) (c) −8 −6 −4 −2 0 2−4−3−2−101234 x 10 Compliant piezoelectric C = 0.01 GPa e = 3.1 C/m є d = 15 є V gs’ V gs’ = - = V gs’ = - a a a σ sp = 0 C/m t = 0.5 nm(b) −0.2 −0.1 0 0.1−202 x 10 a V (V) V gs’ = - a a a a Fig. 7. a) I d versus V gs curves at V ds = C = mV/dec SS (inset) are obtained as compared to a passive gate dielectric. b) Load line characteristics to explain the hysteresis with gate biasvoltages V ′ gs , c) The calculated hysteresis in the transfer curve I d versus V gs for forward and reverse sweeps is shown for a GaN channel piezoFET. based on the Euler-Lagrange equations of motion (see support-ing document for details). For this analysis, we define a free-energy G in units of J/m for the piezoelectric-semiconductorstack: G ( σ m , V ′ gs ) = R V dσ m + R ψ s dσ m − σ m V ′ gs , where V isthe voltage drop across the gate insulator and ψ s is the surfacepotential. Minima in this free-energy landscape correspond tostable charge solutions of the non-linear system. If there aremultiple minima, the actual solution σ m = qn s depends onthe previous state, or the history of the system.For example, Fig. 6(a) shows the load lines and the corre-sponding evolution of the free-energy landscape for different V ′ gs are shown in Fig 6(b). The shape of the energy landscapechanges with the applied voltage. There are two energyminima in the range − . < V ′ gs < . V, and a singleminimum otherwise. Let us assume that there is no charge tobegin with on the capacitor, and ramp the gate from a negative to a positive voltage. Until around V ′ gs = + 0.35 V, the systemremains in the minimum corresponding to the lower chargestate ( ∼ . × /cm ) shown as a blue dot in Fig. 6(a) andthe inset of Fig. 6(b). But when V ′ gs > . V it is driven intothe higher charge state shown as a black dot. Thus, provided V ′ gs < . V, the transistor displays no hysteresis in its I − V characteristics.It is pertinent here to note an important difference inthe nature of negative capacitance of the piezoelectric andferroelectric insulators. The ferroelectric capacitor possessesnegative capacitance at zero charge, whereas the capacitanceof the piezoelectric capacitor is positive at zero charge. Thisproperty of the ferroelectric capacitor is exploited in achieving SS < mV/decade, since the semiconductor load line canintersect the negative capacitance regime of the ferroelectriccharacteristic at the very low charge densities corresponding to subthreshold operation of the transistor. Can a similar negativecapacitance be obtained in the SS regime ( V ′ gs < V) usingpiezoelectric gates? We explore this by tuning the piezoelectricmaterial properties.We find that if a lower stiffness, highly compliant piezo-electric barrier with C ∼ mV/decadeand also boost the on-current. This is shown in Fig. 7(a).Here negative capacitance is accessed in the subthresholdregion, shown by the operating point a in the load linecharacteristics at V ′ gs = -0.05 V shown in Fig. 7(b). Theon-state operation of this transistor corresponds to the highercharge state determined by the operating point a in theload line characteristics at V ′ gs = V ′ gs sweep, as shown in the I d − V gs characteristics in Fig. 7(c)which is calculated using the Lagrangian method. Hysteresis isundesirable in purely switching applications, but desirable formemory. Further, the strain in the higher charge states a , a isvery close to , which is not feasible in realistic materials.If suitable new piezoelectric materials with ultra-low C andhigh e could be developed (see Supporting Informationfor various piezoelectrics with different C and e ), sub- mV/decade switching can be achieved with hysteresiswith suitable choice of semiconductors. Investigation of othertransistor designs incorporating the piezoelectric barrier, suchas the quantum metal transistor [26] to eliminate the hysteresisand reduce strain could be the focus of future work.IV. C ONCLUSION
We also emphasize that we have assumed linear piezoelec-tric parameters in this work to keep the model simple andyet capture the new physics. The non-linear material responseneeds to be explored in future. To conclude, the behaviorof transistor switches using active piezoelectric gate barrierswas explored. Because of electrostriction and piezoelectricity,negative capacitance is predicted to appear in a piezoelectriccapacitor. Using this negative capacitance and a ballistic trans-port model, we predict that compliant piezoelectric barrierscan boost the gate capacitance and increase the on-currentsof transistors. Also, steep switching with sub-60 mV/decadesubthreshold slope is predicted when the negative capacitanceof the piezoelectric barrier is accessed in the off-state operationof the transistor, and this steep behavior is predicted to beassisted by hysteresis based on the Lagrangian method ofstability of the transistor system.A
CKNOWLEDGMENT
This work was supported by the Center for Low EnergySystems Technology (LEAST), one of six centers of STAR-net, the Semiconductor Research Corporation (SRC) programsponsored by MARCO and DARPA.R
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Supporting InformationTransistor Switches using Active Piezoelectric Gate Barriers
S1. σ m − V RELATION OF PIEZOELECTRIC CAPACITOR WITH σ sp Following the same notation as the main text, the 4 th order charge versus voltage σ m − V relation of an electromechanicalcapacitor is C V = σ m − σ sp + ( σ sp − e ) ǫ d C σ m − ǫ d C σ m + e ( ǫ d C ) σ m . (S1)The right side is a fourth order polynomial in σ m , and captures the electromechanical coupling physics. Writing σ m = qn m where n m is the sheet charge density on the metal and σ sp = qn sp = 0 , the polynomial factorizes to C V = qn sp (1 − n m n + α )( n m n − α − − n m n η )(1 + n m n η ) , (S2)where n + α = ( n π + p n π − n sp n π ) / , n − α = ( n π − p n π − n sp n π ) / , qn π = ǫ d C /e , and qn η = √ ǫ d C . Thefour roots are characteristic sheet densities determined uniquely by the electromechanical coefficients and the spontaneouspolarization of the dielectric material. If n π > n sp which is met if C > n sp e /ǫ d , then all four roots are real. The effectof spontaneous polarization σ sp = is a voltage offset, which leads to left and right shifts of the qn m − V characteristics(black and red curves) with respect to the characteristic (blue curve) with σ sp = , as shown in Fig. S1. These shiftswill move the threshold voltages of a corresponding transistor, and will also locally change the slopes of the charge-voltagecharacteristics. −8 −6 −4 −2 0 2 4 6−3−2−10123 x 10 V (V) n m ( c m - ) Piezoelectric C = 1 GPa e = 3.1 C/m ε d = 15 ε Dielectric σ sp = 0 C/m σ sp = 0.2 C/m σ sp = -0.2 C/m Right shiftLeft shift t = 0.5 nm Fig. S1. Charge-voltage ( qn m − V ) characteristics of an electromechanical capacitor with piezoelectric barrier. Color lines (black, blue and red) show thecharacteristics of capacitors for σ sp = , 0 C/m , and -0.2 C/m . σ sp = leads to horizontal left and right shifts of qn m − V curve. S2. B
ALLISTIC
FET I-V
MODEL
When no drain voltage is applied, carriers in the semiconductor are in thermal equilibrium with the source and drainreservoirs, which for a parabolic 2D bandstructure means qn s = C sc V th ln (1 + exp[( E F s − E c ) /kT ]) . From the energy banddiagram of metal-piezoelectric-semiconductor stack of a transistor (Fig. S2), the voltage division qV ′ gs = qV + ( E F s − E c ) translates to the dimensionless equation, e VgsVth = e qF ( ns ) C Vth ( e qnsCqVth − , (S3)where we have defined F ( n s ) = n sp (1 − n s n + α )( n s n − α − − n s n η )(1+ n s n η ) . This equation must be solved to find the semiconductorcharge n s at a gate voltage V gs . If the dielectric is piezoelectric but does not have spontaneous polarization, one must replace F ( n s ) by F pz ( n s ) = n s (1 − n s n η )(1 + n s n η )(1 − n s n π ) to find the semiconductor charge in response to the gate voltage. This isthe major change to a standard Natori-type ballistic FET model [1] brought about by the piezoelectric gate barrier.When a drain voltage V ds is applied, the carrier distribution in the ‘top-of-the-barrier’ point x max in the energy band diagramis split in two. In the ballistic limit of transport, the right-going carriers are in equilibrium with the source reservoir of Fermienergy E F s , whereas the left-going carriers are in equilibrium with the drain reservoir E F d , and they are out of equilibriumby E F s − E F d = qV ′ ds . Note that E F s = E F s ; the application of a drain bias causes a rearrangement of the carrier distribution
PiezoelectricSemiconductorS D E C E Fs G V gs V ds qV gs ’ qφ B qV ΔE C I d t L V gs ’ R d R s Metal
E(k)E Fs E g E c (x)E v (x)x max qV ds ’ E Fd k y k x v g (K)E Fs E Fd Fig. S2. Schematic cross section of a transistor (“piezoFET”) with a piezoelectric gate barrier, semiconductor channel such as Si, GaN or 2D material,MoS and source and drain ohmic contacts. Energy band diagram for the metal-piezoelectric-semiconductor stack of the transistor. For transistor operation,we use ballistic transport model to calculate the transistor characteristics. The mobile sheet carrier density at the ‘top-of-the-barrier’ in energy band diagramis controlled by V gs through the piezoelectric gate barrier, and source and drain Fermi levels E F s & E F d are separated by V ds . Dashed circle shows the k -space for carrier distributions at V ds = 0 and grey circle shows the k -space for carrier distributions at applied V ′ ds i.e. E F s − E F d = qV ′ ds . v g ( k ) is thegroup velocity of carriers. Here, V ′ ds = V ds − I d ( R s + R d ) , where R s and R d are the source and drain contact resistances. in the semiconductor channel. However, with good electrostatic design, one can ensure that the net carrier density at x max isthe same as when V ′ ds = 0 . The carrier distribution in the k − space is depicted in Fig. S2; the dashed circle is the distributionfor V ′ ds = 0 , and the gray half-circles are the result of application of a drain bias, both in the T → K limit. Defining η s = ( E F s − E c ) /kT , v d = V ′ ds /kT , we find that for maintaining the same carrier density, one must meet the condition qn s = C q V th ln(1 + e η s )(1 + e η s − v d ) , which yields η s = ln[ q (1 + e v d ) + 4 e v d ( e qnsCqVth − − (1 + e v d )] − ln[2] (S4) Drain voltage, V ds (V) D r a i n c u rr e n t , I d ( m A / μ m ) BallisticGaN channel300K V gs = C = 1 GPa e = 3.1 C/m є d = 15 є σ sp = 0 C/m t = 0.5 nmDielectric I on ~ 7%= - Fig. S3. Output characteristics depicts the drain current I d versus V ds at gate bias voltage V gs = Note that this is of a similar form as the seminal result on ballistic transistors by Natori et al [1], but the factor n s insidethe square root must be obtained from Eq. S3 to account for the electromechanical coupling self-consistently. By summing Piezoelectric C (GPa) e (C/m ) ReferencesAlN 375 1.5 [2]ScAlN 3.1 [2]125ZnO 218 1.32 [3, 4 ]InN 182 0.43 [4]PZT5H 117 23.3 [4]PMN-PT 105 12.2 [5]PDMS 0.00030.0003 [9]e (C/m ) C ( G P a ) −6 −4 −2 −4 −2 Parylene [6](Polymer)InN [4] ZnO [3, 4]AlN [2]ScAlN [2] PZT [4]PDMS [9] PMN-PT [5]Cellular Polypropylene [8] } Rubber EMFi(Polypropylene) [7] MFC [6] MFC(Macro-fiber composite)Cellular Polypropylene 0.00040.002 [8]EMFi(Polypropylene) 0.006 0.00009 [7]Parylene(polymer) 2.8 0.006 [6]30 10.6 [6]
Fig. S4. Piezoelectric Materials with C and e coefficients. Table for different C and e coefficients of various piezoelectrics with correspondingreferences. C and e values are obtained by literature review from listed references. e is extracted from a matrix relation of [ e ] = [ C ] ∗ [ d ] where [ e ] (unit: C/m ) is the piezoelectric coefficient matrix, [ C ] (unit: N/m ) is the elastic stiffness matrix, [d] (unit: C/N) is the piezoelectric coupling matrix. Thesematrices have sparsity pattern depends on the symmetry of the crystal. However, here in order to get an estimation of the magnitude of e , we use a simplerrelation e (C/m ) = C (N/m ) ∗ d (C/N), in cases where e is not quoted in references. The arrow shows the desired piezoelectric materials to beused for gate barriers of steep transistors. over the group velocities of the k − states, the net current per unit width of the ballistic piezoFET is then given by the sameexpression as in Natori [1]: J = J (cid:16) F ( η s ) − F ( η s − η d ) (cid:17) (S5)where J = qg s g v √ m ⋆ ( kT ) π ~ , and F is the Fermi-Dirac integral of order / .The above expressions provide the complete electrical characteristics of a ballistic piezoFET at any temperature in a compactmodel. We can obtain n s at any gate voltage V gs fully accounting for the electromechanical coupling by solving Eq. S3. Wethen find η s at any given V gs and V ds using Eq. S4, and finally find the drain current per unit width using Eq. S5. Fig. S3shows the output characteristics depicting I d − V ds at different V gs for GaN channel transistors with a compliant piezoelectric(solid lines) and passive dielectric (dashed lines) barriers.Fig. S4 describes different piezoelectric materials with C and e coefficients obtained by literature review from Refs. [2],[3], [4], [5], [6], [7], [8], [9]. Compliant piezoelectric materials with parameter space such as lower C (higher compliance),and higher e (higher piezoelectricity), shown by the arrow in Fig. S4 are useful for gate barriers of proposed steep transistors.S3. E NERGY LANDSCAPE FOR PIEZOELECTRIC - SEMICONDUCTOR STACK : C
OMPUTATIONAL D ETAILS
A. Definition of Free-Energy
Consider the circuit in Fig. S5, showing a piezoelectric-semiconductor stack connected to a voltage source via a resistor R (units: Ω cm ). Both the piezoelectric insulator and semiconductor have non-linear charge ( σ m ) - voltage ( V ) characteristics,denoted say by V = V ins = f ( σ m ) and ψ s = f ( σ m ) respectively. A systematic method of studying the behavior of circuitswith non-linear elements uses the Euler-Lagrange equations [10]: L ( σ m , ˙ σ m ) = T ′ − U (S6) U ( σ m ) = Z σ m f (˜ σ m ) d ˜ σ m + Z σ m f (˜ σ m ) d ˜ σ m (S7) dσ m dt (cid:16) ∂ L ∂ ˙ σ m (cid:17) − ∂ L ∂σ m = V ′ gs − R ˙ σ m , (S8) C sc C PE V gs’ Ψ s System +- R Fig. S5. Schematic of a system shows a piezoelectric-semiconductor stack, represented by a series combination of piezoelectric capacitance C PE andsemiconductor capacitance C sc connected to V ′ gs via a resistor R . ψ s is the channel surface potential at the insulator-semiconductor interface. where L ( σ m , ˙ σ m ) is the Lagrangian, T ′ ( ˙ σ m ) is the magnetic co-energy (in any inductors) and U ( ˙ σ m ) is the potential energyin the capacitors in the circuit. For the circuit in Fig. S5, T ′ = 0 , and we have f ( σ m ) + f ( σ m ) = V ′ gs − R ˙ σ m , (S9)which under equilibrium ( ˙ σ m = 0 ) gives V ′ gs = f ( σ m ) + f ( σ m ) . To determine whether σ m is a point of stable/unstableequilibrium, we write σ m = σ m + δσ m for a small perturbation δσ m , expand the Lagrangian as a Taylor series (upto secondorder) about σ m , and analyze whether the perturbation grows or decays with time: ˙ δσ m = − f ′ ( σ m )+ f ′ ( σ m ) R δσ m = − δσ m /τ (S10) δσ m ( t ) = δσ m exp( − t/τ ) . (S11)where f ′ ( σ m ) is the derivative of f ( σ m ) w.r.t σ m . The system is stable to perturbations if δσ m ( t ) → as t → , i.e. if f ′ ( σ m ) + f ′ ( σ m ) > . The above discussion motivates the definition of the free-energy G ( σ m ) : G ( σ m , V ′ gs ) = Z σ m [ f (˜ σ m ) + f (˜ σ m )] d ˜ σ m − σ m V ′ gs . (S12)From the carrier density expression in a semiconductor channel, ψ s can be expressed as ψ s = f ( ˜ σ m ) = V th ln (cid:16) e ˜ σmCscVth − (cid:17) . Using the expressions of ψ s and V ins = f ( ˜ σ m ) in Eq. S12, the free energy G (unit: J/m ) is found tobe G = α σ m + α σ m + α σ m + α σ m + V th Z σ m ln (cid:16) e ˜ σmCscVth − (cid:17) d ˜ σ m − σ m V ′ gs , (S13)where α = e C ( ǫ d C ) , α = C ǫ d C , α = ( σ sp − e )3 C ǫ d C , α = C are material and geometric constants of the problem.Note the internal energy is a non-linear function of the sheet charge σ m , and is a linear function of applied gate bias voltage V gs . Then, all points of equilibrium satisfy ∂G/∂σ m = 0 , and further, points of stable equilibrium satisfy ∂ G/∂σ m > . B. Self-consistent solution
We make use of the Euler-Lagrange equation to calculate the I − V characteristics of the PiezoFET. The basic structure ofthe self-consistent algorithm involves an outer loop that determines the voltage drop across the intrinsic FET (i.e eliminatingthe voltage drops across the contacts). Inside this loop, we require the charge n s for the intrinsic gate voltage. To do this,we solve the Euler-Lagrange equation (using the implicit Euler method for about τ ) to determine a good guess of charge n s,guess at the present voltage, starting from the value of n s obtained at a previous voltage. n s,guess is then used in a fixedpoint iteration scheme to determine n s , from which the current is finally calculated. We have not encountered prior use of thisEuler-Lagrange method for the calculation of hysteretic characteristics of electron device systems in an extensive literaturesearch, and intend to publish the detailed procedure in a follow-up report.R EFERENCES[1] K. Natori, “Ballistic metal-oxide-semiconductor field effect transistor,”
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