A.A.J. de Lange

An optimal floating-point pipeline CMOS CORDIC processor

The authors present a VLSI CORDIC processor which is obtained using the hierarchical and interactive design methodology on which the DELFT VLSI synthesis is built. They also present an optimized (floating-point) CORDIC algorithm, the hierarchical mapping of this algorithm on a floating-point architecture, the design method, the layout, the chip, and its performance. Algorithm, architecture, and layout are parameterized with respect to the accuracy of rotation angles and vectors. The CORDIC chip is a pipeline that performs 10/sup 7/ plane rotations/s and is mounted in a 144-pin package. The vector entries are 21 bit floating-point numbers (16-bit mantissa and 5 bit exponent in twos complement).<<ETX>>

Design and implementation of a floating-point quasi-systolic general purpose CORDIC rotator for high-rate parallel data and signal processing

The authors describe the design and implementation of an algorithm and a processor which can be used to accelerate computations in which large amounts of rotations (circular as well as hyperbolic) are involved. The processor is a low-cost high-throughput VLSI implementation of the algorithm. With 10/sup 7/ rotations per second, many real-time and interaction-time applications in scientific computation become feasible. The required storage and/or silicon area is low and the execution time is independent of the particular operation performed. Another feature of this CORDIC design is its pipelined architecture and floating point extension. It is angle-pipelinable at the bit-level and has an execution time which is independent of any possible operation that can be executed.<<ETX>>

The synthesis and implementation of signal processing applications specific VLSI CORDIC arrays

A number of high-speed multiprocessor applications of a fast custom VLSI floating-point pipeline CORDIC processor are presented. The applications are concerned with speech processing, matrix arithmetic, antenna array processing, and computer graphics. The applications are designed using an interactive high-level functional design environment for multiprocessor systems and are implemented on a testbed for high-speed parallel processor arrays.<<ETX>>

Real time application of the floating point pipeline CORDIC processor in massive-parallel pipelined DSP algorithms

A number of high-speed multiprocessor applications of a fast custom VLSI floating-point pipeline CORDIC processor are presented. The applications are concerned with speech processing, matrix arithmetic, antenna array processing, and computer graphics. The applications are designed using an interactive high-level functional design environment for multiprocessor systems and are implemented on a test bed for high-speed parallel processor arrays.<<ETX>>

A hierarchical constraint graph generation and compaction system for symbolic layout

A novel approach and system for graph-oriented layout compaction for large symbolic layout designs is presented. Hierarchical compaction is performed by generating geometrical interfaces for compacted subcells which are used as rigid nodes in graphs at higher hierarchical levels. Further reduction of the complexity of graph generation and compaction is achieved by setting only local constraints in the graphs, which requires an iterative graph-generation/compaction scheme.<<ETX>>

An application specific IC for digital signal processing: the floating point pipeline CORDIC processor

Describes concepts, design and implementation of a Coordinate Rotation Digital Computer (CORDIC) processor element that can be used in processor arrays for high-speed processing. The processor is intended to achieve maximal throughput m-matrix computations. It is a systolic processor that performs plane rotations in two different coordinate systems.<<ETX>>

A New Model for the High Level Description and Simulation of VLSI Networks

A new applicative model is presented for the description and analysis of both synchronous and asynchronous VLSI networks at the top levels of abstraction. The model is based on two powerful paradigms, the Applicative State Transition concept of Backus [1] for the descriptive aspects and the theory of single token time(d) Petri Nets [2] [3] [4] for the communicative aspects of the model. These combined paradigms provide an elegant and fast method for the high level description and simulation of VLSI networks.

A hierarchical graph oriented compaction system for symbolic layout

A new graph-oriented compaction system is presented for large symbolic layout designs. True hierarchical compaction is performed by first generating geometrical interface for compacted subcells which are used in graphs at higher hierarchical levels. Among other things, technology independence is achieved by defining constraint graphs for leaf cells (contacts, transistors, etc.) for each different technology, which can be instantiated in the constraint graphs of more complex cells (invertor, full adder, etc.). Further reduction of the complexity of graph generation and compaction is achieved by setting only local constraints in the graphs, which requires an iterative graph-generation/compaction scheme. The compaction algorithm performs a bidirectional breadth-first search through the graph to position layout edges in the critical path and distribute slack.<<ETX>>A new graph-oriented compaction system is presented for large symbolic layout designs. True hierarchical compaction is performed by first generating geometrical interface for compacted subcells which are used in graphs at higher hierarchical levels. Among other things, technology independence is achieved by defining constraint graphs for leaf cells (contacts, transistors, etc.) for each different technology, which can be instantiated in the constraint graphs of more complex cells (invertor, full adder, etc.). Further reduction of the complexity of graph generation and compaction is achieved by setting only local constraints in the graphs, which requires an iterative graph-generation/compaction scheme. The compaction algorithm performs a bidirectional breadth-first search through the graph to position layout edges in the critical path and distribute slack. >

A model for the high-level description and simulation of VLSI networks

An applicative state transition (AST) model for the description and analysis of synchronous and asynchronous VLSI networks at the top levels of abstraction is presented. The model, which uses two powerful paradigms that provide an elegant, fast method for the high-level description and simulation of VLSI networks, explicitly represents the flow of information through a network. This is done by embedding the AST concept into the theory of Petri nets and using Petri net theory to define the communication protocol between nodes. It allows the description of both synchronous and asynchronous designs from the level of abstract functional or algorithmic behaviour down to the register-transfer level. In design descriptions, the model logically separates state, function, and function control, increasing the clearness of the description and simplifying the development and application of silicon compilers. As an application the design of a simple priority queue as both a real-time systolic (synchronous) system and a real-time wavefront (asynchronous) system is explored. This example demonstrates the capability of the AST graph model to handle loops in the design. The model has been embedded in an interactive design system called HIFI (Hierarchical Interactive Flowgraph Integration).<<ETX>>

Hierarchical parameterized synthesis of semi regular VLSI processor arrays

The authors describe a system for the synthesis of semi-regular processor arrays. They discuss the generation of control and memory for the initialization of the feedback loops of the processors in a processor array, and for the rerouting of I/O data from the array boundaries to specific I/O processors in the array. Moreover, they deal with the mapping of a parameterized or full-size processor array to a reduced-size processor array architecture as well as the generation of the necessary control and memory that is involved in this.<<ETX>>