A. Agarwal

Effect of annealing environment on the memory properties of thin oxides with embedded Si nanocrystals obtained by low-energy ion-beam synthesis

The effect of annealing in diluted oxygen versus inert environment on the structural and electrical characteristics of thin silicon dioxide layers with embedded Si nanocrystals fabricated by very low-energy silicon implantation (1 keV) is reported. Annealing in diluted oxygen increases the thickness of the control oxide, improves the integrity of the oxide and narrows the size distribution of the nanocrystals without affecting significantly their mean size (∼2 nm). Strong charge storage effects at low gate voltages and enhanced charge retention times are observed through electrical measurements of metal-oxide-semiconductor capacitors. These results indicate that a combination of low-energy silicon implants and annealing in diluted oxygen allows for the fabrication of improved low-voltage nonvolatile memory devices.

Nickel silicidation on n and p-type junctions at 300°C

The electrical and materials properties of ∼20nm nickel silicide films, formed at 300°C, on n+∕p and p+∕n junctions are investigated. The sheet resistance of the silicide on p+∕n junctions is found to be more than twice as high as that of the silicide on n+∕p junctions. Cross section transmission electron microscopy, Rutherford backscattering spectroscopy, and x-ray photoelectron energy spectroscopy reveal that a pure Ni2Si layer forms on n+∕p junctions while a thicker Ni2Si∕NiSi double layer (∼60% Ni2Si) forms on p+∕n junctions. But the electrical differences are found to correlate only with differences in grain size and dopant concentration in the silicide.

Evaluation of high dose, high energy boron implantation into Cz substrates for epi-replacement in CMOS technology

We implanted high energy boron to create a heavily doped ground plane in Cz wafers in order to replace p/p/sup +/ episubstrates in deep submicron complementary metal-oxide semiconductor (CMOS) technology. Devices manufactured on Cz wafers with a 1.5 or 1.6 MeV, 1/spl times/10/sup 15/ cm/sup -2/ boron implanted ground plane have superior latch-up immunity as compared to devices on epiwafers. Improvements in latch-up suppression were observed for all isolation spacings. Diode leakage was lower in high dose buried-layer substrates than in episubstrates, while gate oxide integrity was equivalent. For the first time, buried layer substrates have been shown to duplicate or exceed the performance of episilicon simultaneously for all relevant CMOS transistor and circuit parameters.

Rapid Thermal Processing of Silicon Wafers with Emissivity Patterns

Fabrication of devices and circuits on silicon wafers creates patterns in optical properties, particularly the thermal emissivity and absorptivity, that lead to temperature nonuniformity during rapid thermal processing (RTP) by infrared heating methods. The work reported in this paper compares the effect of emissivity test patterns on wafers heated by two RTP methods: (1) a steadystate furnace or (2) arrays of incandescent lamps. Method I was found to yield reduced temperature variability, attributable to smaller temperature differences between the wafer and heat source. The temperature was determined by monitoring test processes involving either the device side or the reverse side of the wafer. These include electrical activiation of implanted dopants after rapid thermal annealing (RTA) or growth of oxide films by rapid thermal oxidation (RTO). Temperature variation data are compared with a model of radiant heating of patterned wafers in RTP systems.

Effects of annealing conditions on charge storage of Si nanocrystal memory devices obtained by low-energy ion beam synthesis

The structural and electrical characteristics of thin silicon dioxide layers with embedded Si nanocrystals are reported fabricated by low-energy silicon implantation and with subsequent annealing in inert and diluted oxygen. Thermal treatment in diluted oxygen increases the thickness of the control oxide, does not affect significantly the size of the nanocrystals, and improves the integrity of the oxide. As a result, strong charge storage effects at low gate voltages and enhanced charge retention times are observed through electrical measurements of MOS capacitors. These results indicate that a combination of low-energy silicon implants and annealing in diluted oxygen permits the fabrication of low-voltage nonvolatile memory devices.

Electrical characterization of NiSi/Si interfaces formed by a single and a two-step rapid thermal silicidation

This paper investigates the electrical characteristics of NiSi Schottky barrier diodes (SBD). A single-step rapid thermal process (RTP) and a two-step RTP were employed to form the SBDs. The diode structures were designed so as to minimize edge leakage. The two-step silicidation process resulted in a significant reduction of the reverse leakage current density, suggesting an improvement of the interface characteristics. Temperature-dependent current–voltage measurements were used to analyse the interface characteristics. The two-step RTP process reduces the density of non-ideal micro-contacts with low barrier height, which are responsible for the reverse leakage current.

Dopant redistribution induced by Ni silicidation at 300/spl deg/C

The dopant (arsenic and boron) redistribution induced by Ni silicidation at 300/spl deg/C is investigated by cross-section transmission electron microscopy and secondary ion mass spectroscopy. The dopant segregation at silicide/Si interface is observed. Also a high concentration dopant peak near silicide surface is revealed and attributed to void layer formation due to Kirkendall voiding effect and volume reduction after silicidation. The re-segregation during the conversion from Ni/sub 2/Si to NiSi contributes an extra boron peak in the middle region of the formed silicide film on P+/N Si.

Arsenic redistribution induced by low-temperature Ni silicidation at 450°C on shallow junctions

Redistribution of arsenic (As) during silicidation of a 13-nm Ni film on an n+/p junction at 450°C is investigated. NiSi formation is observed by x-ray diffraction, micro-Raman scattering spectroscopy, and Rutherford backscattering spectroscopy (RBS). Both secondary ion mass spectroscopy and RBS data indicate the redistribution and accumulation of As into two layers after the low-temperature annealing. The deeper accumulation peak, located just near the silicide/silicon interface, is attributed to As segregation from silicide into Si substrate. The shallower accumulation peak is located in a vacancy-cluster layer several nanometers below the silicide film surface. The vacancy-cluster layer, characterized by cross-sectional transmission electron microscopy, separates the silicide film into two layers, and is attributed to the well-known Kirkendall effect.