A. Bardi

A VLSI processor for fast track finding based on content addressable memories

We describe a VLSI processor for pattern recognition based on content addressable memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. A large CAM bank stores all trajectories of interest and extracts the ones compatible with a given event. This task is naturally parallelized by a CAM architecture able to output identified trajectories, recognized among 2/sup 96/ possible combinations, in just a few 40 MHz clock cycles. We have developed this device (called the AMchip03 processor) for the silicon vertex trigger (SVT) upgrade at CDF using a standard-cell VLSI design methodology. This approach provides excellent pattern density, while sparing many of the complexities and risks associated to a full-custom design. On the other hand, the cost performance ratio is well more than one order of magnitude better than an FPGA-based design. This processor has a flexible and easily configurable structure that makes it suitable for applications in other experimental environments. We look forward to share this technology.

The fast tracker processor for hadronic collider triggers

Perspective for precise and fast track reconstruction in future hadronic collider experiments are addressed. We discuss the feasibility of a pipelined highly parallelized processor dedicated to the implementation of a very fast algorithm. The algorithm is based on the use of a large bank of pre-stored combinations of trajectory points (patterns) for extremely complex tracking systems. The CMS experiment at LHC is used as a benchmark. Tracking data from the events selected by the level-1 trigger are sorted and filtered by the Fast Tracker processor at a rate of 100 kHz. This data organization allows the level-2 trigger logic to reconstruct full resolution tracks with transverse momentum above few GeV and search secondary vertexes within typical level-2 times.

Silicon vertex tracker: a fast precise tracking trigger for CDF

The Silicon Vertex Tracker (SVT), currently being built for the CDF II experiment, is a hardware device that reconstructs 2-D tracks online using measurements from the Silicon Vertex Detector (SVXII) and the Central Outer Tracker (COT). The precise measurement of the impact parameter of the SVT tracks will allow, for the first time in a hadron collider environment, to trigger on events containing B hadrons that are very important for many studies, such as CP violation in the b sector and searching for new heavy particles decaying to b . In this report we describe the overall architecture, algorithms and the hardware implementation of the SVT.

The fast tracker processor for hadron collider triggers RID C-4866-2008

Perspectives for precise and fast track reconstruction in future hadron collider experiments are addressed. We discuss the feasibility of a pipelined highly parallel processor dedicated to the implementation of a very fast tracking algorithm. The algorithm is based on the use of a large bank of pre-stored combinations of trajectory points, called patterns, for extremely complex tracking systems. The CMS experiment at LHC is used as a benchmark. Tracking data from the events selected by the level-1 trigger are sorted and filtered by the Fast Tracker processor at an input rate of 100 kHz. This data organization allows the level-2 trigger logic to reconstruct full resolution tracks with transverse momentum above a few GeV and search for secondary vertices within typical level-2 times.

The CDF online silicon vertex tracker

The CDF Online Silicon Vertex Tracker (SVT) reconstructs 2D tracks by linking hit positions measured by the Silicon Vertex Detector to the Central Outer Chamber tracks found by the eXtremely Fast Tracker (XFT). The system has been completely built and assembled and it is now being commissioned using the first CDF run II data. The precision measurement of the track impact parameter will allow triggering on B hadron decay vertices and thus investigating important areas in the B sector, like CP violation and B(s) mixing. In this paper we briefly review the architecture and the tracking algorithms implemented in the SVT and we report on the performance of the system achieved in the early phase of CDF run II.

First steps in the silicon vertex trigger upgrade at CDF

The silicon vertex trigger (SVT) in the CDF experiment at Fermilab performs fast and precise track finding and fitting at the second trigger level and has been a crucial element in data acquisition for Run II physics. However as luminosity rises, multiple interactions increase the complexity of events and thus the SVT processing time, reducing the amount of data CDF can record. The SVT upgrade aims to increase the SVT processing power to restore at high luminosity the original CDF DAQ capability. We describe the first steps in the SVT upgrade, consisting of a new associative memory with 4 times the number of patterns, and a new track fitter to take advantage of these patterns. We describe the system, its tests and its performance

The CDF Silicon Vertex Tracker: Online precision tracking of the CDF Silicon Vertex Detector

SummaryThe Silicon Vertex Tracker is the CDF online tracker which will reconstruct 2D tracks using hit positions measured by the Silicon Vertex Detector and Central Outer Chamber tracks found by the extremely Fast Tracker. The precision measurement of the track impact parameter will allow triggering on events containing B hadrons. This will allow the investigation of several important problems in B physics, like CP violation and Bs mixing, and to search for new heavy particles deca ying to bb.

A large associative memory system for the CDF level 2 trigger

A large Associative Memory system for on-line track reconstruction in a hadron collider experiment has been designed, prototyped and tested. This is the first such application of the Associative Memory concept and it is based on a full custom VLSI chip developed within this project. The Associative Memory is the heart of the Silicon Vertex Tracker, which is part of the Level 2 trigger of the CDF experiment, and is able to complete track finding in the CDF silicon vertex detector less then 1 /spl mu/sec after detector readout is over. This system is a multi-board project running on a common 30 MHz clock, but critical parts multiply clock frequency to operate up to 120 MHz. The Associative Memory board architecture, design, implementation and test are described. The main characteristics of this project are the use of sophisticated clock distribution techniques and the high density of components.

Initial experience with the CDF SVT trigger

The Collider Detector at Fermilab (CDF) Silicon Vertex Tracker (SVT) is a device that works inside the CDF Level 2 trigger to find and fit tracks in real time using the central silicon vertex detector information. SVT starts from tracks found by the Level 1 central chamber fast trigger and adds the silicon information to compute transverse track parameters with offline quality in about . The CDF SVT is fully installed and functional and has been exercised with real data during the spring and summer 2001. It is a complex digital device of more than 100 VME boards that performs a dramatic data reduction (only about one event in a thousand is accepted by the trigger). Diagnosing rare failures poses a special challenge and SVT internal data flow is monitored by dedicated hardware and software. This paper briefly covers the SVT architecture and design and reports on the SVT building/commissioning experience (hardware and software) and on the first results from the initial running.

A pipeline of associative memory boards for track finding RID C-4866-2008

We present a pipeline of associative memory boards for track finding, which satisfies the requirements of level two triggers of the next Large Hadron Collider experiments. With respect to previous realizations, the pipelined architecture warrants full scalability of the memory bank, increased bandwidth (by one order of magnitude), and increased number of detector layers (by a factor of two). Each associative memory board consists of four smaller boards, each containing 32 programmable associative memory chips, implemented with a low-cost commercial field-programmable gate array (FPGA). FPGA programming has been optimized for maximum efficiency in terms of pattern density, while printed circuitboard design has been optimized in terms of modularity and FPGA chip density. A complete associative memory board has been successfully tested at 40 MHz; it can contain 7.2/spl times/10/sup 3/ particle trajectories.