A. Bhasin

Implementation of the ALICE Trigger System

The ALICE trigger system consists of the Central Trigger Processor (CTP) and 24 Local Trigger Units (LTU) that act as a uniform interface to sub-detector front-end electronics. The CTP generates three levels of hierarchical hardware triggers - L0, L1 and L2. At any time, the 24 sub-detectors of the ALICE experiment are dynamically partitioned into up to 6 independent clusters. Trigger selection includes the past-future protection a fully programmable hardware mechanism of controlling the event pile-up. The system contains a number of options that enhance the testability: the SnapShot memories both emulate logic inputs and monitor the logic operation - they enable on-line and in situ detection of system malfunction; more than 1200 signal counters, with simple on-line access, monitor the system performance and check the consistency; the ScopeProbe option enables a direct oscilloscope access to the system inputs, outputs and relevant internal signals. Some of the common CTP functions - down-scaling of trigger classes, synchronization of trigger inputs, etc. - have been realized in a way that is economical on logic resources and offers performance benefits. The implementation of those options using the FPGAs is the main topic of the presentation.

Timing in the ALICE trigger system

In this paper we discuss trigger signals synchronisation and trigger input alignment in the ALICE trigger system. The synchronisation procedure adjusts the phase of the input signals with respect to the local Bunch Crossing (BC) clock and, indirectly, with respect to the LHC bunch crossing instant. The synchronisation delays are within one clock period: 0-25 ns. The alignment assures that the trigger signals originating from the same bunch crossing reach the processor logic in the same clock cycle. It is achieved by delaying signals by an appropriate number of full clock periods. We propose a procedure which will allow us to find alignment delays during the system configuration, and to monitor them during the data taking.

Results on strangeness production from the NA57 experiment

A review of recent NA57 results on K0S and hyperon production from Pb?Pb collisions at 40 and 158 A GeV/c is presented. An energy and centrality dependence of particle yields, strangeness enhancements as well as transverse mass spectra at mid-rapidity are discussed.A review of recent NA57 results on K 0 S and hyperon production from Pb-Pb collisions at 40 and 158 A GeV/c is presented. An energy and centrality dependence of particle yields, strangeness enhancements as well as transverse mass spectra at mid-rapidity are discussed.

LVDS tester: a systematic test of cable signal transmission at the ALICE experiment

In the ALICE experiment, the Low-Voltage Differential Signalling (LVDS) format is used for the transmission of trigger inputs from the detectors to the Central Trigger Processor (CTP), the L0 trigger outputs from Local Trigger Units (LTU) boards back to the detectors and the BUSY inputs from the sub-detectors to the CTP. ALICE has designed a set-up, called the LVDS transmission tester, that aims to measure various transmission quality parameters and the bit-error rate (BER) for long period runs in an automatic way. In this paper, this method is described and the conclusions from these tests for the ALICE LVDS cables are discussed.

Recent developments on the ALICE central Trigger processor

The ALI CE Central Trigger Processor has been constructed and tested, and will shortly be installed in the experimental area. In this review, we introduce the new developments in hardware and software, present a measurement of the minimum propagation time, and illustrate various trigger applications.