A. F. Basile

Capacitance-voltage and deep-level-transient spectroscopy characterization of defects near SiO2/SiC interfaces

Metal-oxide-semiconductor (MOS) interfaces on n-type 4H and 6H-SiC annealed in nitric oxide (NO) for various times were electrically characterized by high-frequency capacitance-voltage and deep-level-transient spectroscopy (DLTS) measurements. Different types of traps were distinguished by DLTS based on the energy-resolved DLTS spectra and comparing DLTS spectra from the two polytypes. Oxide traps, found at much higher densities in the larger bandgap 4H-SiC, are reduced by NO annealing, and their capture behavior is analytically modeled with a tunneling-dependent capture rate. An interface trap distribution is found in 6H-SiC MOS centered at 0.5 eV below the conduction band. Near interface traps in the SiC within 0.1 eV below the conduction band edge, detected at equal concentrations in both polytypes, are not passivated by NO annealing.

Deep level defects in n-type GaAsBi and GaAs grown at low temperatures

Deep level defects in n-type GaAs1−xBix having 0 < x < 0.012 and GaAs grown by molecular beam epitaxy (MBE) at substrate temperatures between 300 and 400 °C have been investigated by Deep Level Capacitance Spectroscopy. Incorporating Bi suppresses the formation of an electron trap with activation energy 0.40 eV, thus reducing the total trap concentration in dilute GaAsBi layers by more than a factor of 20 compared to GaAs grown under the same conditions. We find that the dominant traps in dilute GaAsBi layers are defect complexes involving AsGa, as expected for MBE growth at these temperatures.

Electron trapping in 4H-SiC MOS capacitors fabricated by pre-oxidation nitrogen implantation

Incorporation of nitrogen (N) atoms by ion implantation prior to oxidation of SiO2/4H-SiC interfaces has been investigated by capacitance-voltage (C-V) characteristics and constant capacitance deep-level-transient spectroscopy (CCDLTS) measurements. The shift of the C-V curves to negative voltages can be explained by the partial activation of implanted N atoms during oxidation. The maximum amplitude of the CCDLTS spectra, proportional to the density of near-interface oxide traps, decreases with increasing N dose, but remains significantly larger than that of SiO2/SiC interfaces fabricated by post oxidation annealing in nitric oxide (NO). Intrinsic defects in the SiC epi-layer associated with implantation damage are also observed in N-implanted samples. In contrast, electron traps energetically close to the SiC conduction band, detected in NO annealed samples and presumably introduced during oxidation, are not observed in N-implanted samples. The improved transport characteristics of MOS transistors fabric...

Effect of NO Annealing on 6H- and 4H-SiC MOS Interface States

The electrical properties of the SiC/SiO2 interface resulting from oxidation of the n-type 6H-SiC polytype were studied by hi-lo CV, temperature dependent CV and constant capacitance deep level transient spectroscopy (CCDLTS) techniques. Several trap species differing in energy and capture cross section were identified. A trap distribution at 0.5 eV below the 6H-SiC conduction band energy and a shallower density of states in both the 6H and 4H polytyes are passivated by post-oxidation NO annealing. However, other ultra-shallow and deeper defect distributions remain after nitridation. The latter may originate from semiconductor traps.

Electron Trapping in 4H-SiC MOS Capacitors Fabricated by Sodium-Enhanced Oxidation

The electrical properties of the SiO2/SiC interface fabricated by sodium-enhanced oxidation (SEO) of n-type 4H-SiC were studied by temperature-dependent C-V and constant-capacitance deep level transient spectroscopy (CCDLTS). With the exception of near-interface traps in the SiC epi-layer, which are not present in the SEO samples, the trap species observed in SEO capacitors are the same as those observed in both standard-oxidized and NO-annealed MOS capacitors. Total electron trapping in accumulation is comparable in SEO and NO-annealed capacitors; however, the traps in SEO capacitors are located at the interface whereas tunneling into oxide traps is observed in NO-annealed samples. A series of bias-temperature stress tests show that electron trapping is essentially unchanged when mobile sodium ions are moved toward the interface. The improved mobility attained by this process compared to NO annealing may be due to the absence of near-interface SiC traps in SEO samples.

Comment on “Broadening of metal-oxide-semiconductor admittance characteristics: Measurement, sources, and its effects on interface state density analyses” [J. Appl. Phys. 110, 114115 (2011)]

Low-temperature capacitance-voltage (C-V) characteristics of n-type In0.53Ga0.47As metal-oxide-semiconductor (MOS) capacitors, presented by Paterson et al. [J. Appl. Phys. 110, 114115 (2011)], are modeled by analytical and numerical calculations of the capacitance taking into account the slow response of neutral donors and interface traps to the measurement test signal. This model provides an explanation for the absence of the dip near flat band in the high frequency C-V characteristics, contrary to the prediction based on the ideal MOS capacitance. These calculations also show that a broad energy distribution of interface-traps can explain the broadening of the C-V curve.

Near-interface Traps in n-type SiO 2 /SiC MOS Capacitors from Energy-resolved CCDLTS

Silicon Carbide (SiC) Metal-Oxide-Semiconductor (MOS) capacitors, having different nitridation times, were characterized by means of Constant Capacitance Deep Level Transient Spectroscopy (CCDLTS). Electron emission was investigated with respect to the temperature dependence of emission rates and the amplitude of the signal as a function of the filling voltage. The comparison between the emission activation energies of the dominant CCDLTS peaks and the filling voltages, led to the conclusion that the dominant trapping behavior originates in the Silicon-dioxide (SiO 2 ) layer. Moreover, a model of electron capture via tunneling can explain the dependence of the CCDLTS signal on increasing filling voltage.

Electron trapping at interface states in SiO 2 /4H-SiC and SiO 2 /6H-SiC MOS capacitors

The SiO2/SiC interface limits optimum SiC MOSFET performance due to a high density of interface states (DIT), which is reduced in devices that receive post-oxidation NO-annealing. Also, the interface state density in the 6H polytype is generally lower, approaching that of the NO treated 4H [1]. In this work, interface states are investigated in both as-oxidized (AO) and NO-annealed (NO) MOS capacitors fabricated from n-type epitaxial (0001) 4H- and 6H-SiC. Oxidation was done in dry O2 at 1150°C followed by 30 min in Ar ambient. The NO exposure was at 1175°C for 2h. Constant capacitance deep level transient spectroscopy (CCDLTS) results are compared with the DIT from hi-lo C-V and temperature dependent C-V measurements [2].

Effects of antimony (Sb) on electron trapping near SiO2/4H-SiC interfaces

To investigate the mechanism by which Sb at the SiO2/SiC interface improves the channel mobility of 4H-SiC MOSFETs, 1 MHz capacitance measurements and constant capacitance deep level transient spectroscopy (CCDLTS) measurements were performed on Sb-implanted 4H-SiC MOS capacitors. The measurements reveal a significant concentration of Sb donors near the SiO2/SiC interface. Two Sb donor related CCDLTS peaks corresponding to shallow energy levels in SiC were observed close to the SiO2/SiC interface. Furthermore, CCDLTS measurements show that the same type of near-interface traps found in conventional dry oxide or NO-annealed capacitors are present in the Sb implanted samples. These are O1 traps, suggested to be carbon dimers substituted for O dimers in SiO2, and O2 traps, suggested to be interstitial Si in SiO2. However, electron trapping is reduced by a factor of ∼2 in Sb-implanted samples compared with samples with no Sb, primarily at energy levels within 0.2 eV of the SiC conduction band edge. This trap ...

Effects of N Incorporation on Electron Traps at SiO2/SiC Interfaces

Temperature dependent capacitance-voltage (C-V) and constant capacitance transient spectroscopy (CCDLTS) measurements have been performed to investigate the role of N in improving the transport properties of 4H-SiC MOS transistors. The higher channel mobility in the N pre-implanted transistors is due at least in part to activation of a small fraction of the implanted N near the SiO2/SiC interface as donors in SiC during oxidation, thus reducing the effects of interface trapping. In addition, the absence of oxidation-induced near-interface defects, which were observed in NO-annealed capacitors, may contribute to the improved mobility in N pre-implanted transistors.