A. J. De Groot

Sprint - The Systolic Processor with a Reconfigurable Interconnection Network of Transputers

The Systolic Processor with a Reconfigurable Interconnection Network of Transputers (SPRINT) is a sixty-four-processor multiprocessor developed at Lawrence Livermore National Laboratory for experimentally evaluating systolic algorithms and architectures. This paper describes the architecture of the SPRINT and several algorithms which have been executed on it.

Systolic Implementation Of Neural Network

The backpropagation algorithm for error gradient calculations in multilayer, feed-forward neural networks is derived in matrix form involving inner and outer products. It is demonstrated that these calculations can be carried out efficiently using systolic processing techniques [3], particularly using the SPRINT, a 64-element systolic processor developed at Lawrence Livermore National Laboratory. This machine contains one million synapses, and forward-propagates 12 million connections per second, using 100 watts of power. When executing the algorithm, each SPRINT processor performs useful work 97% of the time. The theory and applications are confirmed by some nontrivial examples involving seismic signal recognition.

High-performance parallel processors based on star-coupled WDM optical interconnects

As the performance of individual elements within parallel processing systems increases, increased communication capability between distributed processor and memory elements is required. There is great interest in using fiber optics to improve interconnect communication beyond that attainable using electronic technology. Several groups have considered WDM, star-coupled optical interconnects. In this paper, we propose a fiber optic transceiver to provide low latency, high bandwidth channels for such interconnects using a robust multimode fiber technology. We use instruction-level simulation to quantify the bandwidth, latency, and concurrency required for such interconnects to scale to 256 nodes, each operating at I GFLOPS performance. We show that performance scales to /spl ap/100 GFLOPS for scientific application kernels using a small number of wavelengths (8 to 32), only one wavelength received per node, and achievable optoelectronic bandwidth and latency.

A Systolic Array For Efficient Execution Of The Faddeev Algorithm

The Systolic Processor with a Reconfigurable Interconnection Network of Transputers (SPRINT) is a sixty-four-element multiprocessor developed at Lawrence Livermore National Laboratory to evaluate systolic algorithms and architectures experimentally. The processors are interconnected in a reconfigurable network which can emulate networks such as the two-dimensional mesh, the triangular mesh, the trapezoidal mesh, the tree, and the shuffle-exchange network. The SPRINTs computation capability surpasses its communication capability. Techniques have been developed to perform the Faddeev Algorithm utilizing most of its computing capability by operating on block matrices. These techniques reduce communication bandwidth requirements for a given computation rate and increase efficiency to close to 100%. The Faddeev algorithm calculates the quantity CX+D, where X is the solution to AX=B and where A, B, C and D are given. All quantities are square matrices. Several linear algebra operations such as the matrix-matrix product and matrix inversion can be calculated by loading appropriate values for A, B, C, and D. The Faddeev algorithm is executed on the SPRINT to compare theory with experiment.

Visualization techniques for molecular dynamics

Electron and X-ray diffractometry visualize atoms in severely stressed single-crystal silicon and help analyze the resulting phase transformations. Massively parallel computers simulate both diffraction techniques. We study these phase transitions with a number of simulation techniques. We calculate the position of the atoms in the material during the process and display atomic images of the crystal structure as a function of time. Simulated diffraction patterns enable us to follow structural transformations more easily. In addition, we have developed several diagnostic imaging techniques that aid the analysis of phase transformations: the pair-correlation function, bar-code plotting, ring statistics and subvolume visualization. >

Simulation of mechanical deformation via nonequilibrium molecular dynamics

We are developing two- and three-dimensional pair-force and embedded-atom simulations of mechanical deformation processes-indentation, machining, and inelastic ballistic-impact collisions-related to current nanometer machining practice. Here we describe these problems and their implementation using both mainframe and parallel-processor computers.

A systolic array for efficient execution of the radon and inverse radon transforms

The Systolic Processor with a Reconfigurable Interconnection Network of Transputers (SPRINT) [1] is a sixty-four-element multiprocessor developed at Lawrence Livermore National Laboratory to evaluate systolic algorithms and architectures experimentally. The processors are interconnected in a reconfigurable network which can emulate networks such as the two-dimensional mesh, the triangular mesh, the tree, and the shuffle-exchange network. New systolic algorithms and architectures are described which perform the Radon transform [8] and inverse Radon transform with efficiency arbitrarily close to 100%. High efficiency is possible with any connected network topology, even with low communication bandwidth. The results of the algorithms executed on the SPRINT compare closely with theory.

Crashworthiness simulations with DYNA3D

Current progress in parallel algorithm research and applications in vehicle crash simulation is described for the explicit, finite element algorithms in DYNA3D. Problem partitioning methods and parallel algorithms for contact at material interfaces are the two challenging algorithm research problems that are addressed. Two prototype parallel contact algorithms have been developed for treating the cases of local and arbitrary contact. Demonstration problems for local contact are crashworthiness simulations with 222 locally defined contact surfaces and a vehicle/barrier collision modeled with arbitrary contact. A simulation of crash tests conducted for a vehicle impacting a U-channel small sign post embedded in soil has been run on both the serial and parallel versions of DYNA3D. A significant reduction in computational time has been observed when running these problems on the parallel version. However, to achieve maximum efficiency, complex problems must be appropriately partitioned, especially when contact dominates the computation.

Computing The Two Dimensional Fast Fourier Transform On A General Purpose Mesh Connected Multiprocessort

This paper discusses an implementation of the two dimensional fast Fourier transform (FFT) on SPRINT, the Systolic Processor with a Reconfigurable Interconnection Network of Transputers. SPRINT is a 64 element multiprocessor developed at Lawrence Livermore National Laboratory for the experimental evaluation of systolic algorithms and architectures. The implementation is a radix two decimation in time algorithm, valid for an arbitrary sized p x q mesh of processors and an arbitrary sized P x Q complex input array (P, Q, p, and q must all be powers of two). The processors are interconnected with their nearest neighbors along North-South-East-West communication links. The problems of array partitioning, bit reversal, subarray transform computation, and weighted (butterfly) combinations are all discussed. Finally, benchmark results are presented, and speedup and efficiency are discussed.

Efficient bit-level, word-level, and block-level systolic arrays for matrix-matrix multiplication

This paper investigates the mapping of matrix-matrix multiplication onto bit level, word level and block level systolic arrays. Highly efficient and regular bit level, word level and block level systolic arrays are described. Efficiencies of many block level and word level systolic arrays reported in this paper approach 100%, three times the efficiencies of systolic arrays reported previously. Bit level systolic arrays reported in this paper require less computation time than than do bit level systolic arrays reported previously and, for special matrices, require less cells. Execution times of block level systolic algorithms on a sixty-four-element multiprocessor agree with theory.