A.J. Magrath

Design and implementation of a FPGA sigma-delta power DAC

In this paper we discuss the design and implementation of a FPGA power DAC for digital audio applications. The paper concentrates on the sigma-delta modulator, which is used to convert an oversampled PCM input signal into a 1-bit code suitable for controlling a power switch. The design of the bit-flipping architecture used to reduce the pulse-repetition frequency of the output is discussed, together with the the loop filter structure and transfer function design. This is followed by details of FPGA architecture and the optimisations required for implementation.

Performance enhancement of sigma-delta modulator D-A converters using non-linear techniques

A new non-linear algorithm is presented for enhancing the performance of 1-bit sigma-delta modulator digital-to-analogue converters. The basis of the technique is to modify the operation of the quantizer in the loop so that a high pass quantization error is produced. This provides additional attenuation of quantization noise in the baseband, giving an increase in resolution synonymous with an increase in loop order. The algorithm is analysed and shown to be equivalent to a particular class of adaptive modulator. Furthermore, it is shown that the new algorithm has improved linearity over the standard modulator.

A sigma-delta modulator topology with high linearity

A /spl Sigma//spl Delta/ modulator topology is presented which achieves high linearity by modifying the transfer function of the quantizer in the loop. It is applicable to both A-D and D-A converters. Particular implementation advantages are gained in the A-D case because no random noise source is required. Results are presented which show also that, in comparison to conventional quantizer dithering, the scheme has excellent dynamic range properties.

A use of sigma-delta modulation in power digital-to-analogue conversion

Power digital-to-analogue (D–A) converters have applications in digital audio, portable equipment and industrial control systems. This paper discusses the use of sigma–delta modulation as the primary processing block in power D–A systems. The focus is on the pulse repetition frequency (PRF) of the one-bit output and its suitability for power switching. It is shown that in order to preserve high power efficiency and tolerance to a non-ideal output stage, the PRF of the output may be reduced and made constant by the use of a technique termed bit flipping. The performance of different bit flipping algorithms is discussed which aim to regulate the PRF whilst maintaining the stability of the modulation process. Results are presented which compare the performance of the different systems under the conditions of an ideal and a non-ideal output stage.

Efficient coding of linear predictive coefficients for wideband speech

This paper considers the coding of the linear predictive (LP) filter coefficients for applications where the highest quality natural-sounding speech reproduction is required. Bandwidths as high as 16 kHz and linear prediction orders of 38 are considered. To deal with the increase in model order, a method is proposed to code the trajectory of the line-spectral pair (LSP) representation of the LP coefficients. To improve the performance of the system, a hybrid scheme is proposed which utilises a combination of intra-frame LSP coding and trajectory-based coding. This scheme exploits the reduced sensitivity of the human auditory system to distortion at higher frequencies.

Parallel interconnection of cascaded subfilters: improved performance at high order

This paper describes a class of IIR digital filter structures that make a compromise between standard cascade and parallel structures. Synthesis algorithms are described and the results of bit level, fixed point simulations that compare two variants of new structures are presented. Results demonstrate that both structures exhibit superior noise performance than the cascade form, and that their synthesis is numerically more robust than the parallel form, giving improved overall performance.

Digital-domain dithering of sigma-delta modulators using bit flipping

A new technique is presented for dithering single-bit sigma-delta modulator (SDM) analog-to-digital and digital-to-analog converters (ADCs and DACs) in the digital domain. The system operates by detecting and randomizing the limit cycles responsible for baseband tones. The system is efficient to realize in hardware and avoids the implementation problems of analog dither required in conventional SDM ADCs.

High quality audio coding for mobile multimedia communications

Publisher Summary This chapter highlights the growing importance of research into audio to the fast-moving field of mobile multimedia. The main body of this chapter presents results from two projects that examine high-quality, low bit-rate coding of audio, both music and speech. One approach uses wavelets, which offer advantages over polyphase filter banks and discrete cosine transform (DCT) in MPEG music coding at low bit rates. The other approach uses the long established linear predictive coding (LPC) technique, but in a modified guise, with orders significantly greater than 10. It also uses least mean squares techniques to fit lines in time-frequency space to the line spectral pair (LSP) representation of LPC. The first section offers an introduction to audio coding and processing in the broadest sense as is applicable to mobile multimedia. This chapter emphasizes that in a complete mobile multimedia (MMM) system, the designer needs to take account of more than just the most effective coding technique. Following this, a new approach to speech coding is described and some experimental results presented. Some attention is paid to the means by which high-quality, high-order LPC speech may be resynthesized. Finally, the principles of the use of wavelets in audio coding are covered and these too are supported by results.