A. Kandasamy

Analog CMOS peak detect and hold circuits. Part 1. Analysis of the classical configuration

Peak detectors (peak-detect-and-hold circuits, PDHs) are a key element in nuclear electronics signal processing and have been incorporated as a fully integrated block in several front-end readout chips. In CMOS designs, the PDH uses an MOS current source as the rectifying element inside the feedback loop of a high-gain amplifier. However, the nonidealities in the amplifier and feedback elements significantly limit its accuracy and stability. This paper reports on the limits of the classical CMOS PDH. Static errors due to offset, finite gain, and commonmode rejection, dynamic errors due to parasitic capacitive coupling and slew rate, and loop stability are analyzed. Expressions for each error source and consequent design tradeoffs between accuracy, speed, and dynamic range, and driving capability are derived. In a related article (Part 2), a two-phase PDH configuration, which overcomes the major limits of the classical approach is presented. r 2002 Elsevier Science B.V. All rights reserved.

Analog CMOS peak detect and hold circuits. Part 2. The two-phase offset-free and derandomizing configuration ☆

An analog CMOS peak detect and hold (PDH) circuit, which combines high speed and accuracy, rail-to-rail sensing and driving, low power, and buffering is presented. It is based on a configuration that cancels the major error sources of the classical CMOS PDH, including offset and common mode gain, by re-using the same amplifier for tracking, peak sensing, and output buffering. By virtue of its high absolute accuracy, two or more PDHs can be used in parallel to serve as a data-driven analog memory for derandomization. The first experimental results on the new peak detector and derandomizer (PDD) circuit, fabricated in 0.35mm CMOS technology, include a 0.2% absolute accuracy for pulses with 500 ns peaking time, 2.7 V linear input range, 3.3 mW power dissipation, 250 mV/s droop rate, and negligible dead time. The use of such a high performance analog PDD can greatly relax the requirements on the digitization in multi-channel systems. r 2002 Elsevier Science B.V. All rights reserved.

Front-end electronics for the RatCAP mobile animal PET scanner

We report on the development of the front-end electronics for rat conscious animal positron emission tomography (RatCAP), a portable and miniature positron emission tomography scanner. The application-specific integrated circuit (ASIC) is realized in a complementary metal-oxide-semiconductor 0.18 /spl mu/m technology and is composed of 32 channels of charge sensitive preamplifier, third-order semi-Gaussian bipolar shaper, timing discriminator with independent channel adjustable threshold, and a 32-line address serial encoder to minimize the number of interconnections between the camera and the data acquisition system. Each chip has a maximum power dissipation of 125 mW. A mathematical model of the timing resolution as a function of the noise and slope at the discrimination point as well as the photoelectron statistics was developed and validated. So far, three ASIC prototypes implementing part of the electronics were sent to fabrication. Results from the characterization of the first two prototypes are presented and discussed.

Analog peak detector and derandomizer for high rate spectroscopy

A compact and accurate readout system has been developed for high-rate spectroscopy with multi-element detectors. The fully self-triggered system multiplexes the signals from 32 detectors into a novel peak detector, which also serves as a derandomizer. The captured pulse heights are stored as analog samples before being presented to the ADC along with the corresponding channel addresses. The peak detector incorporates a new two-phase configuration that cancels offsets and other errors found in conventional designs. Offset cancellation gives the peak detector rail-to-rail sensing and driving capability, and permits two or more peak detectors to be operated in parallel to serve as a data-driven analog memory. First experimental results on the new peak detector and derandomizer (PDD) circuit, fabricated in 0.35 /spl mu/m CMOS technology, include a 0.2% absolute accuracy for pulses with 500 ns peaking time, 2.7 V linear input range, 3.5 mW power dissipation, 250 mV/s droop rate, and negligible dead time. We have tested the system with 32 CZT detectors and a /sup 241/Am source. The spectra collected from the 32-channel system show that the noise performance of the preamp/shaper is not degraded by the multiplexing, peak detecting, and derandomizing operations.

Amplitude and time measurement ASIC with analog derandomization: first results

We describe a new amplitude specific integrated circuit (ASIC) for accurate and efficient processing of high-rate pulse signals from highly segmented detectors. In contrast to conventional approaches, this circuit affords a dramatic reduction in data volume through the use of analog techniques (precision peak detectors and time-to-amplitude converters) together with fast arbitration and sequencing logic to concentrate the data before digitization. In operation the circuit functions like a data-driven analog first-in, first-out (FIFO) memory between the preamplifiers and the analog-to-digital converter (ADC). Peak amplitudes of pulses arriving at any one of the 32 inputs are sampled, stored, and queued for readout and digitization through a single output port. Hit timing, pulse risetime, and channel address are also available at the output. Prototype chips have been fabricated in 0.35 micron CMOS and tested. First results indicate proper functionality for pulses down to 30 ns peaking time and random input rates up to 1.6 MHz on a single channel. Amplitude accuracy of the peak detect and hold circuit is 0.3% (absolute). TAC accuracy is within 0.3% of full scale. Power consumption is less than 2 mW/channel at the maximum counting rate. Compared with conventional techniques such as track-and-hold and analog memory, this new ASIC will enable efficient pulse height measurement at 20 to 300 times higher rates.

The PDD ASIC: highly efficient energy and timing extraction for high-rate applications

The peak detector derandomizer ASIC provides threshold discrimination, arbitration, peak and timing detection with analog memory, sparsification, and multiplexing for 32 input channels of analog pulse data. In this work the ASIC is characterized for high-rate operation. A new version of the ASIC, can process multiple events occurring at the same time and provides time-over-threshold measurement for pile up rejection.

The RatCAP conscious small animal PET tomography

The RatCAP is a small, head mounted PET tomograph designed and built to image the brain of an awake rat. It allows PET imaging studies to be carried out on laboratory rats without the use of anesthesia, which severely suppresses brain functions and affects many of the neurological activities that one would like to study using PET. The tomograph consists of a 4 cm diameter ring containing 12 block detectors, each of which is comprised of a 4 times 8 array of 2.2 times 2.2 times 5 mm3 LSO crystals read out with a matching APD array. The APDs are read out using a custom designed ASIC and VME readout system. We have successfully performed a system integration test with a partially instrumented tomograph ring. We present the recent progress towards a fully integrated system

Initial performance of the RatCAP, a PET camera for conscious rat brain imaging

The first fully functional prototype of the RatCAP (Rat conscious animal PET) scanner has been constructed and preliminary evaluations have been performed. RatCAP is a miniature, high performance PET scanner designed specifically to image the brain of a rat while directly attached to its head. The goal is to eliminate the need for anesthesia which can confound quantitative brain studies and prevent simultaneous correlations of neurochemistry and behavior. RatCAP is a fully 3D tomograph with a transaxial (axial) field-of-view of 38(18) mm, outside diameter 72 mm, and weight <200 g which is supported by a small tether. A total of 384 LSO crystals are divided among 12 independent detector blocks, each of which contains an avalanche photodiode (APD) photosensor array and a custom-designed ASIC for highly integrated front-end processing. A custom FPGA-based time-stamp module has been designed and implemented, achieving a preliminary system resolution of 13.9 ns FWHM. With a point source in the FOV center, spatial resolution is 2.1 mm FWHM, energy resolution averages 23% FWHM, and sensitivity is 0.7% at an average threshold of 150 keV. Novel offline data processing algorithms have been developed including methods for time and energy calibrations, corrections for physical effects, and a highly accurate iterative image reconstruction. Initial phantom and rat brain images have been obtained

Advanced-readout ASICs for multielement CdZnTe detectors

A generation of high performance front-end and read-out ASICs customized for highly segmented CdZnTe sensors is presented. The ASICs, developed in a multi-year effort at Brookhaven National Laboratory, are targeted to a wide range of applications including medical, safeguards/security, industrial, research, and spectroscopy. The front-end multichannel ASICs provide high accuracy low noise preamplification and filtering of signals, with ver-sions for small and large area CdZnTe elements. They implement a high order unipolar or bipolar shaper, an innovative low noise continuous reset system with self-adapting capability to the wide range of detector leakage currents, a new system for stabilizing the output baseline and high output driving capability. The general-purpose versions include pro-grammable gain and peaking time. The read-out multichannel ASICs provide fully data driven high accuracy amplitude and time measurements, multiplexing and time domain derandomization of the shaped pulses. They implement a fast arbitration scheme and an array of innovative two-phase offset-free rail-to-rail analog peak detectors for buffering and absorption of input rate fluctuations, thus greatly relaxing the rate requirement on the external ADC. Pulse amplitude, hit timing, pulse risetime, and channel address per processed pulse are available at the output in correspondence of an exter-nal readout request. Prototype chips have been fabricated in 0.5 and 0.35 μm CMOS and tested. Design concepts and experimental results are discussed.

Multichannel energy and timing measurements with the peak detector/derandomizer ASIC

The peak detector/derandomizer ASIC (PDD) provides threshold discrimination, peak detection, time-to-amplitude conversion, analog memory, sparsification, and multiplexing for 32 channels of analog pulse data. In this work the spectroscopic capabilities of the chip (high resolution and high rate) are demonstrated along with correlated measurements of pulse risetime. Imaging and coincidence detection using the PDD chip will also be illustrated.