A. Kruth

Timepix3: a 65K channel hybrid pixel readout chip with simultaneous ToA/ToT and sparse readout

The Timepix3, hybrid pixel detector (HPD) readout chip, a successor to the Timepix \cite{timepix2007} chip, can record time-of-arrival (ToA) and time-over-threshold (ToT) simultaneously in each pixel. ToA information is recorded in a 14-bit register at 40 MHz and can be refined by a further 4 bits with a nominal resolution of 1.5625 ns (640 MHz). ToT is recorded in a 10-bit overflow controlled counter at 40 MHz. Pixels can be programmed to record 14 bits of integral ToT and 10 bits of event counting, both at 40 MHz. The chip is designed in 130 nm CMOS and contains 256 × 256 pixel channels (55 × 55 μm2). The chip, which has more than 170 M transistors, has been conceived as a general-purpose readout chip for HPDs used in a wide range of applications. Common requirements of these applications are operation without a trigger signal, and sparse readout where only pixels containing event information are read out. A new architecture has been designed for sparse readout and can achieve a throughput of up to 40 Mhits/s/cm2. The flexible architecture offers readout schemes ranging from serial (one link) readout (40 Mbps) to faster parallel (up to 8 links) readout of 5.12 Gbps. In the ToA/ToT operation mode, readout is simultaneous with data acquisition thus keeping pixels sensitive at all times. The pixel matrix is formed by super pixel (SP) structures of 2 × 4 pixels. This optimizes resources by sharing the pixel readout logic which transports data from SPs to End-of-Column (EoC) using a 2-phase handshake protocol. To reduce power consumption in applications with a low duty cycle, an on-chip power pulsing scheme has been implemented. The logic switches bias currents of the analog front-ends in a sequential manner, and all front-ends can be switched in 800 ns. The digital design uses a mixture of commercial and custom standard cell libraries and was verified using Open Verification Methodology (OVM) and commercial timing analysis tools. The analog front-end and a voltage-controlled oscillator for 1.5625 ns timing resolution have been designed using full custom techniques.

Digital architecture of the new ATLAS pixel chip FE-I4

With the high hit rate foreseen for the innermost layers at an upgraded LHC, the current ATLAS Front-End pixel chip FE-I3 [1] would start being inefficient. The main source of inefficiency comes from the copying mechanism of the pixel hits from the pixel array to the end of column buffers. A new ATLAS pixel chip FE-I4 is being developed in a 130 nm technology for use both in the framework of the Insertable B-Layer (IBL) project and for the outer layers of Super-LHC. FE-I4 is made of 80×336 pixels and features a reduced pixel size of 50×250 μm2. In the current design, a new digital architecture is introduced in which hit memories are distributed across the entire pixel array and the pixels organized in regions. In this paper, the digital architecture of FE-I4 is presented as well as the complete data flow.

Architectural modeling of pixel readout chips Velopix and Timepix3

We examine two digital architectures for front end pixel readout chips, Velopix and Timepix3. These readout chips are developed for tracking detectors in future high energy physics experiments. They must incorporate local intelligence in pixels for time-over-threshold measurement and sparse readout. In addition, Velopix must be immune to single-event upsets in its digital logic. The most important requirements for both chips are pixel size, timing resolution, low power and high-speed sparse readout. We describe the transaction level architectural models of the chips using SystemVerilog. The correctness of the models is ensured using Open Verification Methodology. We will also discuss the advantages gained from transaction level modeling.

GOSSIPO-3: measurements on the prototype of a read-out pixel chip for Micro-Pattern Gaseous Detectors

GOSSIPO-3 is a demonstrator of a front-end chip designed in IBM 130 nm CMOS in collaboration between Nikhef (Amsterdam) and the Physics Department of the University of Bonn for the read-out of Micro-Pattern Gas Detectors. The prototype features charge sensitive amplifiers, discriminators, a high resolution Time to Digital Converter (TDC), two different Low Drop Out (LDO) voltage regulators for supply voltage control of the Time to Digital Converter, biasing circuits and control logic on a 2 × 1 mm2 die. The chip can be operated in a time measuring mode or an event counting mode. Following the prototype announcement at the TWEPP 2009, measurement data on gain, noise performance, channel to channel ToT spread and LDO load step responses is now available. The measurement results confirm the high gain and low noise (ENC = 25 e−) predicted by simulations. Stable and reproducible time bin sizes of the TDC are also confirmed.

Charge Pump Clock Generation PLL for the Data Output Block of the Upgraded ATLAS Pixel Front-End in 130 nm CMOS

FE-I4 is the 130 nm ATLAS pixel IC currently under development for upgraded Large Hadron Collider (LHC) luminosities. FE-I4 is based on a low-power analog pixel array and digital architecture concepts tuned to higher hit rates [1]. An integrated Phase Locked Loop (PLL) has been developed that locally generates a clock signal for the 160 Mbit/s output data stream from the 40 MHz bunch crossing reference clock. This block is designed for low power, low area consumption and recovers quickly from loss of lock related to single-event transients in the high radiation environment of the ATLAS pixel detector. After a general introduction to the new FE-I4 pixel front-end chip, this work focuses on the FE-I4 output blocks and on a first PLL prototype test chip submitted in early 2009. The PLL is nominally operated from a 1.2V supply and consumes 3.84mW of DC power. Under nominal operating conditions, the control voltage settles to within 2% of its nominal value in less than 700 ns. The nominal operating frequency for the ring-oscillator based Voltage Controlled Oscillator (VCO) is fV CO = 640MHz. The last sections deal with a fabricated demonstrator that provides the option of feeding the single-ended 80MHz output clock of the PLL as a clock signal to a digital test logic block integrated on-chip. The digital logic consists of an eight bit pseudo-random binary sequence generator, an eight bit to ten bit coder and a serializer. It processes data with a speed of 160Mbit/s. All dynamic signals are driven off-chip by custommade pseudo-LVDS drivers.

Digital column readout architectures for hybrid pixel detector readout chips

In this paper, two digital column architectures suitable for sparse readout of data from a pixel matrix in trigger-less applications are presented. Each architecture reads out a pixel matrix of 256 x 256 pixels with a pixel pitch of 55 μm. The first architecture has been implemented in the Timepix3 chip, and this is presented together with initial measurements. Simulation results and measured data are compared. The second architecture has been designed for Velopix, a readout chip planned for the LHCb VELO upgrade. Unlike Timepix3, this has to be tolerant to radiation-induced single-event effects. Results from post-layout simulations are shown with the circuit architectures.

SEU tolerant memory design for the ATLAS pixel readout chip

The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. For this design, configuration memories are based on the DICE latches where layout considerations are followed to improve the tolerance to SEU. Tests have shown that DICE latches for which layout approaches are adopted are 30 times more tolerant to SEU than the standard DICE latches. To prepare for the new pixel readout chip planned for the future upgrades, a prototype chip containing 512 pixels has been designed in a 65 nm CMOS process and a new approach is adopted for SEU tolerant latches. Results in terms of SEU and TID tolerance are presented.

GOSSIPO-4: an array of high resolution TDCs with a PLL control

GOSSIPO-4 is a prototype chip featuring an array of high resolution Time to Digital Converters with a PLL control that has been taped out the 9th of August 2011. This prototype is the successor of GOSSIPO-3 test chip and the precursor of the 65k pixel chip TimePix3. The prototype is being developed to test a set of new features that will be used in TimePix3, including a 8 pixel structure sharing one fast oscillator with a new topology, a PLL to provide the control voltage to the oscillators, a custom fast counter and a new small-area cell library.

The design for test architecture in digital section of the ATLAS FE-I4 chip

This paper describes an original Design-for-Test (DfT) architecture implemented in the ATLAS FE-I4 pixel readout System-on-Chip (Soc) to accommodate the higher quality demands of future generation LHC detectors. To ensure that the highest possible number of fault-free devices is used for the detector construction, the so-called production test to detect faulty devices after the manufacturing has to be executed. For that reason, we devised a straightforward and effective DfT circuitry inside the digital part of the FE-I4 that will enable high fault coverage of potential structural faults while maintaining the performance and area penalties of the entire design negligible.

ATLAS FE-I4 ASIC

The ATLAS FE-I4 ASIC is a novel pixel detector readout chip designed in a CMOS 130 nm feature size process. The chip is able to cope with high hit rate and withstand the harsh radiation environment in close proximity to the interaction point at LHC. FE-I4 will find its first application with ATLAS IBL, an additional innermost pixel layer scheduled for installation in 2013, but is also suited for the intermediate radii pixel layers for future upgrades. In this paper, the modular design concept of FE-I4 is introduced and its readout architecture, analog performance and radiation hardness are discussed. After the successful development of the first full-scale prototype version of the chip in 2010, the production version for IBL (FE-I4B) has recently become available. Here, we review the main design choices for FE-I4B and present first testing results.