A. Leger

First-level charged particle trigger for the L3 detector

Abstract A first-level charged particle trigger based on parallel processing and look-up tables has been developed for the L3 detector. It processes analog signals generated by the central tracking detector, a drift chamber with axial wires. The trigger decision is made on the total number of tracks, the number of coplanar pairs of tracks, or on more complicated topologies found in the projection normal to the beam axis. The system is very flexible and can be adjusted to a wide range of background conditions and tracking chamber efficiencies.

SVT: an online silicon vertex tracker for the CDF upgrade

The SVT is an online tracker for the CDF upgrade which will reconstruct 2D tracks using information from the Silicon VerteX detector (SVXII) and Central Outer Tracker (COT). The precision measurement of the track impact parameter will then be used to select and record large samples of B hadrons. We discuss the overall architecture, algorithms, and hardware implementation of the system.

Silicon vertex tracker: a fast precise tracking trigger for CDF

The Silicon Vertex Tracker (SVT), currently being built for the CDF II experiment, is a hardware device that reconstructs 2-D tracks online using measurements from the Silicon Vertex Detector (SVXII) and the Central Outer Tracker (COT). The precise measurement of the impact parameter of the SVT tracks will allow, for the first time in a hadron collider environment, to trigger on events containing B hadrons that are very important for many studies, such as CP violation in the b sector and searching for new heavy particles decaying to b . In this report we describe the overall architecture, algorithms and the hardware implementation of the SVT.

The CDF Silicon Vertex Tracker: Online precision tracking of the CDF Silicon Vertex Detector

SummaryThe Silicon Vertex Tracker is the CDF online tracker which will reconstruct 2D tracks using hit positions measured by the Silicon Vertex Detector and Central Outer Chamber tracks found by the extremely Fast Tracker. The precision measurement of the track impact parameter will allow triggering on events containing B hadrons. This will allow the investigation of several important problems in B physics, like CP violation and Bs mixing, and to search for new heavy particles deca ying to bb.

The ATLAS liquid argon calorimeter read-out system

The Liquid Argon calorimeters play a central role in the ATLAS experiment. The environment at the LHC collider imposes challenging tasks to their read-out system. To achieve measurements of particles and trigger signals at high precision, the detector signals are processed at various stages before reaching the Data Acquisition system (DAQ). Signals from the calorimeter cells are received by front-end boards, which digitize and sample the incoming pulse. Read-out Driver (ROD) boards further process the data at a trigger rate of up to 75 kHz. An optimal filtering procedure is applied to optimize the signal-to-noise ratio. The ROD boards calculate precise energy, time and quality of the detector pulse, which are then sent to the DAQ. In addition, the RODs perform a monitoring of the data. The architecture of the ATLAS Liquid Argon detector read-out is discussed, in particular the design and functionality of the ROD board. Performance results obtained with ROD prototypes as well as experience from complete test setups with final production boards are reported.

Initial experience with the CDF SVT trigger

The Collider Detector at Fermilab (CDF) Silicon Vertex Tracker (SVT) is a device that works inside the CDF Level 2 trigger to find and fit tracks in real time using the central silicon vertex detector information. SVT starts from tracks found by the Level 1 central chamber fast trigger and adds the silicon information to compute transverse track parameters with offline quality in about . The CDF SVT is fully installed and functional and has been exercised with real data during the spring and summer 2001. It is a complex digital device of more than 100 VME boards that performs a dramatic data reduction (only about one event in a thousand is accepted by the trigger). Diagnosing rare failures poses a special challenge and SVT internal data flow is monitored by dedicated hardware and software. This paper briefly covers the SVT architecture and design and reports on the SVT building/commissioning experience (hardware and software) and on the first results from the initial running.

A prototype of programmable associative memory for track finding

We present a device, based on the concept of associative memory for pattern recognition, dedicated to on-line track finding in high-energy physics experiments. A large pattern bank, describing all possible tracks, can be organized into field programmable gate arrays where all patterns are compared in parallel to data coming from the detector during readout. Patterns, recognized among 2/sup 66/ possible combinations, are output in a few 30 MHz clock cycles. Programmability results in a flexible, simple architecture and it allows one to keep up smoothly with technology improvements. A 64 PAM array has been assembled on a prototype VME board and fully tested up to 30 MHz.

The readout system of the ATLAS liquid argon calorimeters

The ReadOut Driver (ROD) system is a key element of the ATLAS Liquid Argon Calorimeters readout system. It processes a predetermined number of samples of the bipolar output waveform from the calorimeter front-end electronics and precisely determines the energy deposited in each calorimeter cell and the timing of these signals at the Level one trigger output rate of 100 kHz. It applies an optimal filtering algorithm while minimizing the pileup and electronic noise and using coefficient constants determined from the calibration. Around 190000 channel outputs are processed through the Liquid Argon ROD system. Only their energy, timing and a quality flag are sent to the data acquisition. The impossibility to recover the original data imposes severe reliability requirements to the ROD system. The system consists of around 200 ROD modules, 200 transition modules and 16 custom-made backplanes. A ROD module receives data from 1024 calorimeter cells through eight 1.6 Gbit/s optical fibers and consists of one mother board with four daughter boards (called processing units) which contain two Digital Signal Processors (DSP) each. This modular design offers the possibility to use the latest development on DSP technology in the future. Two different DSPs have been tested and the results compared. These results together with the description of the Liquid Argon Calorimeters readout system are discussed.

A multi-hit ADC and TDC for the charged particle trigger of the L3 experiment☆

Abstract A Fastbus ADC and TDC module has been developed for the trigger of the L3 experiment. It provides fast and precise integration of successive pairs of charges derived from the charge division wires of the central tracking chamber, as well as a measurement of their drift times. The minimum separation time between digitizations is 170 ns. The charges are measured with a precision of 1 pC up to charges of 600 pC. The drift times are measured in 50 ns time bins. A system including 60 modules provides data allowing the reconstruction of charged particle tracks in three dimensions. This information is used in background rejection algorithms of the second and third level triggers.

Readout electronics development for the ATLAS silicon tracker

Abstract We present the status of the development of the readout electronics for the large area silicon tracker of the ATLAS experiment at the LHC, carried out by the CERN RD2 project. Our basic readout concept is to integrate a fast amplifier, analog memory, sparse data scan circuit and analog-to-digital convertor (ADC) on a single VLSI chip. This architecture will provide full analog information of charged particle hits associated unambiguously to one LHC beam crossing, which is expected to be at a frequency of 40 MHz. The expected low occupancy of the ATLAS inner silicon detectors allows us to use a low speed (5 MHz) on-chip ADC with a multiplexing scheme. The functionality of the fast amplifier and analog memory have been demonstrated with various prototype chips. Most recently we have successfully tested improved versions of the amplifier and the analog memory. A piecewise linear ADC has been fabricated and performed satisfactorily up to 5 MHz. A new chip including amplifier, analog memory, memory controller, ADC, and data buffer has been designed and submitted for fabrication and will be tested on a prototype of the ATLAS silicon tracker module with realistic electrical and mechanical constraints.