A. N. M. Masum Choudhury

Rapid thermal annealing of Be, Si, and Zn implanted GaAs using an ultrahigh power argon arc lamp

The use of a 100‐kW water‐walled dc argon lamp to anneal ion‐implanted GaAs is reported. Annealing cycles of 3 and 10 s and peak temperatures from 950 to 1200 °C have been used to anneal Be, Si, and Zn implanted following representative implant schedules of technological importance. It is demonstrated that this technique is superior to conventional furnace anneal techniques in terms of the doping profiles, peak carrier concentrations, activation efficiencies (particularly at high doses), and mobilities achieved. The annealing technique should be applicable to large volume GaAs integrated circuit production and 100‐mm‐diam wafers can be annealed in a single exposure with better than 2% temperature uniformity (Si data).

Rapid thermal annealing of Se and Be implanted InP using an ultrahigh power argon arc lamp

A 100‐kW water‐walled dc argon arc lamp has been used for the first time to post anneal ion‐implanted InP samples. Temperatures as high as 925 °C and short cycle times (3 and 10 s) are used for the process. Se and Be were ion implanted into room temperature and hot substrate InP samples. A sputter deposited SiO2 layer, 120 mm thick, covering all wafer surfaces was used as an encapsulant during the lamp anneal. Hot substrate Se implants (400 keV, 1.8×1014 cm−2, 200 °C) show an average mobility of 1415 cm2/Vs and an activation of ∼63%, and room‐temperature Be implants (50 keV, 3.35×1013 cm−2 and 150 keV, 5.74×1013 cm−2) an average mobility of 88 cm2/Vs and activation of ∼45%. This annealing technique is straightforward and gives activations and mobilities comparable to, or better than, the best furnace anneals with sharp profiles and simplified surface encapsulation.

Improved activation of Mg+ and As+ dual implants in GaAs by capless rapid thermal annealing

The activation of high dose Mg+ implants (1×1015 cm−2, 100 keV) in GaAs using capless rapid thermal annealing has been improved by the co‐implantation of As+. This technique reduces the outdiffusion of the implanted Mg, which can adversely affect the activation of shallow, high dose implants. Compared with an activation of 18% for an implant of Mg+ only, the co‐implantation of As+ has increased the activation to as much as 61% with concomitant sheet resistance of 136 Ω/⧠. The placement of the As+ implant with respect to the position of the Mg+ profile has been determined to play a role in the activation efficiency. This technique has been applied to the formation of thick p+ regions with high surface carrier concentrations, which has important applications in device fabrication for reduction of contact resistances.

Electrical characteristics of Be‐implanted GaAs diodes annealed with an ultrahigh power argon arc lamp

The potential of arc lamp annealing techniques in GaAs device processing is demonstrated by the fabrication of Be‐implanted mesa pin diodes. Implants were done at 50 and 120 keV with doses of 4.4×1014 and 5.1×1014 cm−2, respectively (total dose =9.5×1014 cm−2) into a 14‐μm‐thick undoped (ND−NA≊7.5×1014 cm−3) GaAs epitaxial layer grown by vapor phase epitaxy. Ten‐second annealing cycles with peak temperatures of 950° and 1050 °C have been studied. The electrical characteristics of these diodes are superior to published furnace‐annealed, Be‐implanted GaAs diodes.

Triple implant (In,Ga)As/InP n-p-n heterojunction bipolar transistors for integrated circuit applications

For the first time (In,Ga)As/InP n-p-n heterojunction bipolar transistors (HJBTs) applicable to integrated circuits have been fabricated by triple ion implantation. The base has been formed by beryllium ion implantation and the collector by silicon ion implantation. The implants were made into an LPE-grown n-n (In,Ga)As/InP heterostructure on an n+-InP substrate. This inverted mode emitter-down heterojunction transistor structure demonstrates to a maximum current gain of 7 with no hysteresis in the characteristics. The ideality factors of the IBversus VBE, and ICversus VBEcharacterisitics with VCB= 0, are 1.25 and 1.08, respectively, indicating that the defect level in the herterojunction is low and that minority-carrier injection and diffusion is the dominant current flow mechanism.

Formation of p‐type GaAs layers using Mg+ implantation and capless rapid thermal annealing

The enhanced overpressure proximity technique has been applied to the formation of p‐GaAs layers using capless rapid thermal annealing of GaAs implanted with Mg+. Carrier concentrations in excess of 1×1019 cm−3 and excellent hole mobilities have been achieved without a dielectric encapsulant using this annealing method. Implants were performed at 200 or 320 keV with doses of 1×1014 cm−2 or 1×1015 cm−2. Hall measurements have yielded electrical activations as high as 86% and 38% for the low and high dose samples, respectively. Capacitance‐voltage measurements on implanted samples indicate that this annealing technique can be used to control the doping profile for use in the fabrication of devices requiring p‐n junctions.

High‐speed 1.3 μm InGaAs/GaAs metal‐semiconductor‐metal photodetector

A high frequency, low dark current, 1.3 μm metal‐semiconductor‐metal photodetector on GaAs is reported. The measured frequency response of this photodetector up to 10 GHz agrees with a model that assumes different collection times for electrons and holes.

Cathodoluminescence observation of metallization‐induced stress variations in GaAs/AlGaAs multiple quantum well structures

Cathodoluminescence scanning electron microscopy is utilized to investigate the stresses present underneath 0.4 μm gold layers deposited on GaAs/AlGaAs multiple quantum well structures grown by molecular beam epitaxy on GaAs substrates. Using the known stress dependence of excitonic lines in quantum wells, the magnitude of stress is determined to be about 1 kbar. The stress‐induced change in the refractive index, attributed to photoelastic effect, is about 0.01 for the structures studied in the present work.

Zn diffusion in GaAs obtained by a simple open‐tube technique

Zn diffusion into 2‐in.‐diam semi‐insulating GaAs wafers has been carried out by a simple, open‐tube diffusion method using a commercially available GaAsZn solid source and without surface coating or encapsulation. High‐quality (μ=75–100 cm2/V s) layers with a flat carrier concentration and sharp cutoff Zn distribution have been obtained. The p‐type layers obtained by this method are uniform across the wafer, and the technique can be easily scaled up. Selective diffusion of Zn was also demonstrated with this technique, using a plasma‐deposited Si3N4 as a diffusion mask.

VA-5 InGaAs/InP heterojunction bipolar transistors for digital integrated circuits

usual wide bandgap emitter. Such devices are inter::;ting for high-speed switching because the wide bandgap col1,;:ctor (as pointed out by Kroemer’): 1) suppresses hole inje,,lion under conditions of saturation and 2 ) allows for colle :toremitter interchangability. For optimum performance of these devices hole injel.1ion form the base into the emitter must be much less than e1et:tron injection from the emitter into the base. E lec t ro luminesc~~~ce , arising from minority-carrier recombination, provides a mcans of determining the relative strength of the electron and hole currents. We have studied these processes by spectrally re ;(llving the lectroluminescence mitted from the mitter-blase junction. We observe strong luminescence arising in the base (mincl :iLtycarrier recombination) with no significant luminescence ar sling in the emitter. The structure investigated included a comimsitionally graded layer between the base and emitter to lelp suppress hole injection. Our results indicate that there is 1 ittle if any injection of holes into the emitter, confirming ’.hat compositional grading has the effect of transferring the b lndgap difference to the valence band thereby significantly enhancing hole confinement. Apart from establishing the relative efficiency for elect : ( m -