A. Ruhan Bevi

FPGA based pipelined architecture for RC5 encryption

The reconfigurable processors like FPGA are extensively used for cryptographic applications which have reduced the time to market of the hardware logic. This paper describes the high performance pipelined hardware implementation of RC5 algorithm in Xilinx Vertex II Pro FPGA with a 12-stage pipeline scheme that has achieved an encryption rate of 6.9 Gbps. The proposed design operates on 12 input data and a common key where each clock signal produces a partial single round encryption output. After 12 clocks cycles, the cipher text of the corresponding input data is derived at the output sequentially for every clock transition. The pipelined hardware was implemented and the efficiency was compared with the other versions of RC5.

FPGA based sliding window architecture for RC5 encryption

In the current scenario, security for the data has more of its concern. Many encryption algorithms have been proposed to satisfy certain levels of security issues and known for their cryptographic strengths. The extensive use of reconfigurable processors like FPGA for cryptographic applications has made the design and testing of hardware logic simple. This paper introduces, a new sliding window based hardware architecture in Xilinx FPGA for RC5 cryptographic algorithm modeled to satisfy the response and waiting time. This is done to provide faster encryption thereby reducing the risk of deadline miss. The performance comparison between implementation of various RC5 architectures based on area and delay are graphed.

Design and investigation of a chaotic neural network architecture for cryptographic applications

Abstract Artificial neural networks are an integral part of emerging technologies, and ongoing research has shown that they can be applied to a variety of applications. This paper proposes a new cryptographic algorithm using chaotic neural networks, whose function is enhanced by construction with polynomials that exhibit chaos, namely, nonlinear Hermite and Chebyshev polynomials. These polynomials incorporate a memristor conductance, which is used as an activation function in the chaotic neural networks. Further, a function of the weights obtained from the chaotic neural networks, is used to generate the initial values that are used in the cryptographic process. The encryption algorithm employed here is inspired by the Lai–Massey block cipher with cubic and two-dimensional logistic maps, and the evaluation of these chaotic equations is performed using correlation values. The correlation values between the cipher and plain text are also examined to determine the undecipherability of the message to be sent on a public channel.

Memristor Based Chaotic Neural Network with Application in Nonlinear Cryptosystem

The global shift towards digitization has resulted in intensive research on Cryptographic techniques. Chaotic neural networks, augment the process of cryptography by providing increased security. In this paper, a description of an algorithm for the generation of an initial value for encryption using neural network involving memristor and chaotic polynomials is provided. The chaotic series that is obtained is combined with nonlinear 1 Dimensional and 2 Dimensional chaotic equations for the encryption process. A detailed analysis is performed to find the fastest converging neural network, complemented by the chaotic equations to produce least correlated ciphertext and plaintext. The use of Memristor in Neural Network as a generator for chaotic initial value as the encryption key and the involvement of nonlinear equations for encryption, makes the communication more confidential. The network can further be used for secure multi receiver systems.

Network Protocol-Based QoS Routing Using Software Defined Networking

Software defined networking (SDN) is an incipient network paradigm in which the control plane is moved out of the individual network nodes and into a separate centralized controller which is capable of exploiting the complete knowledge of the network to optimize flow management. SDN is a promising way to support the dynamic nature of networks at present and in the future. OpenFlow is the most commonly used SDN protocol. OpenFlow protocol governs the communication between SDN controllers and the underlying network infrastructure. Routing not only implies mere forwarding of data packets, but also refers to the choosing of best path for the data traffic based on certain metrics. In this paper, a routing algorithm namely Network Protocol-based QoS Routing is proposed and simulated using the network emulation tool, Mininet. The working of the algorithm is verified to correctness using the network protocol analyser Wireshark. The performance analysis is done by considering the QoS parameters.

Bi primitive switching crypto system with key generation mechanism for secure applications

Ensuring security to the information transaction is a major challenge in the communication environment. The choice to guarantee the data transfer using a ciphering algorithm leads to high cost and complexity. The software-based implementations of cryptographic algorithms are easy to design and operate, but the performance penalty paid is high. The hardware implementations of cryptographic algorithms are considered as a task involving intensive computation and evaluation. Microcontroller-based applications for the same prove to be good solutions to the problem for cost-optimized applications. This paper aims to design, implement, and test a microcontroller (AT89c51)-based crypto system using the Tiny Encryption Algorithm and the Extended Tiny Encryption Algorithm as security primitives. The real-time data can be processed with scheduling of the primitives and the context switching between the primitives reduces the probability of being attacked. The keys for the crypto system are generated using internal timers of the microcontroller. The data to be transmitted are encrypted with any one of the security primitives with the generated key and the encrypted data are transmitted both in wired and wireless modes. At the receiving end, the received data are decrypted and the performance of the crypto system is evaluated on the basis of throughput, code size used, and execution time.

RC5 implementation in ARM platform for cryptographic applications

Due to recent advancements in technology, information security is becoming the biggest challenge to achieve in the field of wireless communications. To ensure secured transmission of data, data is encrypted and decrypted using cryptographic algorithms. The RC5 encryption algorithm is one of those cryptographic algorithms widely used to meet the security demands of the industry. This paper proposes the design and implementation of RC5 algorithm in the ARM 7TDMI processor. The ARM-based implementation enhances the performance of the crypto system with the reduced cost compared to the hardware implementations in FPGA. The testing of the encryption and decryption units with a constant key is communicated using UART module. The analysis of the implementation parameters like code size, execution time of the key expansion module for the RC5 computations are documented. The results show that the code size and the execution time are reduced and tailored for power constraint applications.

High Quality FPGA Optimized Random Number Generator

In this paper we designed a new type of Random number generator by using shift registers and LUT with D-FF as input to it. The algorithm used to generate random numbers is realized using simple xor circuit and implemented on a Virtex II FPGA from Xilinx. This designed block indicate a good sequence of random numbers which is used in high-speed data processor, Testing Instruments, Finding Laser Range, Timeof-flight mass spectrometry experiments etc. The randomness of this type of RNG is tested using NIST statistical test and this method has produced good results.

Performance Analysis of TEA Block Cipher for Low Power Applications

The FPGA based embedded system plays a vital role in the implementation of many cryptographic applications especially in the field of wireless communication. The security constraint applications increasingly demand the encryption process for sensitive data transfer from one end to the other end. The software implementation of security algorithms are easy to implement but it lags in its execution speed and performance. Therefore, hardware implementations are considered to be a good alternate, since they provide additive performance along with the low power and less memory consumption. The Tiny Encryption Algorithm (TEA) is one of the fastest and efficient cryptographic algorithms well suited for many real time data communications with moderate security. This paper analyzes the hardware implementation of TEA in FPGA with different approaches that consumes lesser resources with increased execution speed. This work emphasizes the efficient implementation of TEA algorithm for various applications where the hardware resources are limited and power constraints are stringent.