A.S. Spinelli

How far will silicon nanocrystals push the scaling limits of NVMs technologies

For the first time, memory devices with optimized high density (2E12#/cm/sup 2/) LPCVD Si nanocrystals have been reproducibly achieved and studied on an extensive statistical basis (from single cell up to 1 Mb test-array) under different programming conditions. An original experimental and theoretical analysis of the threshold voltage shift distribution shows that Si nanocrystals have serious potential to push the scaling of NOR and NAND flash at least to the 35 nm and 65 nm nodes, respectively.

Scaling trends for random telegraph noise in deca-nanometer Flash memories

We present a thorough investigation of the random telegraph noise scaling trend for both NAND and NOR floating-gate flash memories, including experimental and physics-based modeling results. The statistical distribution of the random telegraph noise amplitude is computed using conventional 3D TCAD simulations, establishing a direct connection with cell parameters. The analysis results in a simple formula for the random telegraph noise amplitude standard deviation as a function of cell width, length, substrate doping, tunnel oxide thickness and drain bias. All the simulation results are in good agreement with experimental data and are of utmost importance to understand the random telegraph noise instability and to control it in the development of next generation flash technologies.

Ultimate Accuracy for the nand Flash Program Algorithm Due to the Electron Injection Statistics

This paper investigates the ultimate accuracy of the NAND flash program algorithm that is determined by the statistical injection of electrons from the substrate to the floating gate. The granular nature of the electron flow during a constant-current Fowler-Nordheim program operation is shown to spread the programmed threshold-voltage distribution of the array cells. The electron injection statistics displays a Poissonian behavior for low amounts of transferred charge, but a sub-Poissonian character becomes clearly evident when large charge packets are stored. This effect is expected from the reduction of the tunnel oxide field that follows each electron storage event into the floating gate, establishing a correlation among such events. Finally, the impact of the electron injection statistical spread on the accuracy of the NAND flash program algorithm is investigated as a function of the technology node feature size, drawing projections on future NAND technologies.

A new conduction mechanism for the anomalous cells in thin oxide flash EEPROMs

The temperature dependence of the anomalous leakage current in the tail cells of flash memory is investigated on arrays with different oxide thicknesses. It is shown that both the conduction mechanism and the annealing kinetics of the leakage current change when the thickness is reduced below about 8 nm, becoming independent of temperature. The microscopic conduction of the tail cells is analyzed to investigate the conduction model in thin oxides.

Statistical modeling of reliability and scaling projections for flash memories

A new physically-based model for reliability analysis of flash memories is presented. The model provides a quantitative description of the distribution of the stress-induced leakage current (SILC) in large memory arrays, considering the statistics of the defects responsible for the trap-assisted tunneling (TAT) current. Simulation results are in good agreement with SILC statistics over oxide thicknesses of 6.5, 8.8 and 9.7 nm. The model can be used to quantitatively evaluate the failure rate under different conditions and assess the trade-off between oxide thinning and device reliability. The relationship between tunnel oxide scalability and defect concentration is also quantitatively assessed.

A new two-trap tunneling model for the anomalous stress-induced leakage current (SILC) in Flash memories

We present new experimental and numerical results on the leakage current in Flash cells after cycling, showing that two markedly different behaviors can be identified. Most tail cells show a leakage current that can be successfully described by single-trap tunneling. However, the unstable and very high leakage exhibited by a few anomalous cells requires a different explanation. An improved physical model including two-trap tunneling processes can account for the large current enhancement in the anomalous cells, as well as explaining for the first time their asymmetric and erratic behavior.

Program/erase dynamics and channel conduction in nanocrystal memories

We present new models for nanocrystal (NC) memories, addressing program/erase (P/E) transients and carrier conduction in the channel controlled by discrete nodes. The model allows for the calculation of the achievable threshold-voltage (V/sub T/) window and P/E times under uniform tunneling-injection conditions. Comparisons with experimental data are shown, demonstrating that our physically-based model correctly captures the VT dependence on critical cell and bias parameters. The model can be used to draw technological guidelines for window optimization in NC cells.

A new channel percolation model for V/sub T/ shift in discrete-trap memories

In this work we studied the mechanisms for channel conduction in discrete-trap memories (DTMs). It is shown that the threshold voltage V/sub T/ in the cell corresponds to a percolation condition in the channel, where the inverted layers connect source to drain. A numerical model is presented which is able to calculate the local profile of V/sub T/ in the channel, and to evaluate the global V/sub T/ in the cell according to a channel percolation condition. The model is shown to account for the size dependence of V/sub T/ in DTM cells, and for the staircase charge-loss characteristics observed on ultrascaled devices. The implications of the percolation mechanism from the reliability point of view are finally discussed in details.

New technique for fast characterization of SILC distribution in flash arrays

A new method for characterizing the SILC in flash memories is presented. The role of the SILC distribution in determining the failure statistics of flash cell arrays is first pointed out. The new technique is then explained, and results from a test array are shown. The description in terms of a simplified formula for the leakage current provides evidence for the bimodal distribution of the SILC distribution in the memory array under test. The bimodal character of the SILC distribution is finally verified by directly comparing characteristics measured on real cells with results of the new method on the same memory chip.

Defect generation statistics in thin gate oxides

We analyze data-retention experiments for flash memory arrays with thin tunnel oxide (t/sub ox/ = 5 nm). These samples show an additional conduction mechanism besides Fowler-Nordheim tunneling and stress-induced leakage current (SILC). The additional leakage contribution is analyzed with respect to the spatial distribution in the array and the shape of the current-voltage characteristics, and is interpreted as an anomalous SILC due to a two-trap leakage path. From the cycling dependence of the distribution tails related to one- and two-trap leakage, we provide evidence that the defect generation statistics is not Poissonian, but is instead correlated. Possible physical mechanisms responsible for correlated generation are also discussed.