A. Sebastian

Achieving Subnanometer Precision in a MEMS-Based Storage Device During Self-Servo Write Process

In probe-based data storage devices, microelectromechanical system-based microscanners are typically used to position the storage medium relative to the read/write probes. Global position sensors are employed to provide position information across the full scan range of these microscanners. However, to achieve repeatable positioning, it is also necessary to have medium-derived position information. Dedicated storage fields known as servo fields are employed to obtain this medium-derived position information. The servo-patterns on these servo fields have to be written using the global position sensors prior to the regular operation of the storage device by employing a scheme known as ldquoself-servo writerdquo process. During this process, subnanometer positioning resolutions, well below that provided by the global position sensors, are desirable. Such precise positioning at acceptable bandwidth requires the directed design of the closed-loop noise sensitivity transfer function so as to minimize the impact of sensing noise. This paper describes control architectures in which the impact of measurement noise on positioning is minimal while providing satisfactory tracking performance. It is estimated that the positioning error due to sensing noise is a remarkably low 0.25 nm. Experimental results are also presented that show error-free operation of the device at high densities.

Drift-resilient cell-state metric for multilevel phase-change memory

A new cell-state metric is proposed for multilevel phase-change memory (PCM) that is more representative of the fundamental programmed entity, i.e., the amorphous/crystalline phase configuration in the PCM cell. This metric exhibits improved performance in terms of drift and better sensing resolution of cell states with a large amorphous-phase fraction when compared to the conventional low-field resistance metric. Experimental results using PCM test devices of mushroom type demonstrate the efficacy of the new metric.

A Framework for Reliability Assessment in Multilevel Phase-Change Memory

Multilevel-cell (MLC) storage is the preferred way for achieving increased capacity and thus lower cost-per-bit in memory technologies. In phase-change memory (PCM), MLC storage is hampered by noise and resistance drift. In this paper the issue of reliability in MLC PCM devices is addressed at the array level. The purpose of this study is to identify the dominant reliability issues in PCM arrays and to provide a practical methodology to assess the reliability and predict the retention of multilevel states. Experimental data are used to derive and fit simple empirical models which can be used to assess the device reliability over the course of time.

Reliable MLC data storage and retention in phase-change memory after endurance cycling

For phase-change memory to be considered a true universal memory it would have to combine MLC storage, for low cost per bit, with adequately high endurance and at least moderate data retention. However, this appears to be particularly difficult to achieve, because of phenomena such as material segregation, which comes as an effect of cycling, and resistance drift, which is inherent in the amorphous phase and affects the stability of stored data. We present a combination of a memory cell with stable programming behavior over cycling, electrical sensing techniques and signal processing technologies, to demonstrate the viability of reliable, non-volatile, MLC storage in phase-change memory cells after extended endurance cycling.

Estimation of amorphous fraction in multilevel phase change memory cells

The effective thickness of the amorphous chalcogenide part within the active element of a phase change memory (PCM) cell is estimated through electrical measurements. Current-voltage characteristics obtained at various intermediate cell states are fitted with the trap-limited subthreshold transport model and the amorphous part thickness is then extracted. Several cell electrical measures, such as the resistance and the threshold voltage, are shown to closely relate to the estimated parameter. The results serve to further validate the trap-limited conduction model, as well as the series phase distribution hypothesis in the active layer of a PCM cell.

Carbon-Based Resistive Memories

Carbon-based nonvolatile resistive memories are an emerging technology. Switching endurance remains a challenge in carbon memories based on tetrahedral amorphous carbon (ta-C). One way to counter this is by oxygenation to increase the repeatability of reversible switching. Here, we overview the current status of carbon memories. We then present a comparative study of oxygen-free and oxygenated carbon-based memory devices, combining experiments and molecular dynamics (MD) simulations.

Memristive effects in oxygenated amorphous carbon nanodevices

Computing with resistive-switching (memristive) memory devices has shown much recent progress and offers an attractive route to circumvent the von-Neumann bottleneck, i.e. the separation of processing and memory, which limits the performance of conventional computer architectures. Due to their good scalability and nanosecond switching speeds, carbon-based resistive-switching memory devices could play an important role in this respect. However, devices based on elemental carbon, such as tetrahedral amorphous carbon or ta-C, typically suffer from a low cycling endurance. A material that has proven to be capable of combining the advantages of elemental carbon-based memories with simple fabrication methods and good endurance performance for binary memory applications is oxygenated amorphous carbon, or a-CO x . Here, we examine the memristive capabilities of nanoscale a-CO x devices, in particular their ability to provide the multilevel and accumulation properties that underpin computing type applications. We show the successful operation of nanoscale a-CO x memory cells for both the storage of multilevel states (here 3-level) and for the provision of an arithmetic accumulator. We implement a base-16, or hexadecimal, accumulator and show how such a device can carry out hexadecimal arithmetic and simultaneously store the computed result in the self-same a-CO x cell, all using fast (sub-10 ns) and low-energy (sub-pJ) input pulses.Computing with resistive-switching (memristive) memory devices has shown much recent progress and offers an attractive route to circumvent the von-Neumann bottleneck, i.e. the separation of processing and memory, which limits the performance of conventional computer architectures. Due to their good scalability and nanosecond switching speeds, carbon-based resistive-switching memory devices could play an important role in this respect. However, devices based on elemental carbon, such as tetrahedral amorphous carbon or t-aC, typically suffer from a low cycling endurance. A material that has proven to be capable of combining the advantages of elemental carbon-based memories with simple fabrication methods and good endurance performance for binary memory applications is oxygenated amorphous carbon, or a-COx. Here, we examine the memristive capabilities of nanoscale a-COx devices, in particular their ability to provide the multilevel and accumulation properties that underpin computing type applications. We show the successful operation of nanoscale a-COx memory cells for both the storage of multilevel states (here 3-level) and for the provision of an arithmetic accumulator. We implement a base-16, or hexadecimal, accumulator and show how such a device can carry out hexadecimal arithmetic and simultaneously store the computed result in the self-same a-COx cell, all using fast (sub-10 ns) and low-energy (sub-pJ) input pulses.