A. Tasch
University of Texas at Austin
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Featured researches published by A. Tasch.
Applied Physics Letters | 1992
C. Tsai; K.‐H. Li; D. Kinosky; R. Qian; T. Hsu; J. T. Irby; Sanjay K. Banerjee; A. Tasch; Joe C. Campbell; B. K. Hance; J. M. White
The role of silicon hydride species in the photoluminescence intensity behavior of porous Si has been studied. The surfaces of luminescent porous Si samples were converted to a predominate SiH termination using a remote H plasma. The as‐passivated samples were then immersed in various concentrations of hydrofluouric solutions to regulate the recovery of SiH2 termination on the surface. Photoluminescence measurements and transmission Fourier‐transform infrared spectroscopy have shown that predominant silicon monohydride (SiH) termination results in weak photoluminescence. In contrast, it has been observed that the appearance of silicon dihydride (SiH2) coincides with an increase in the photoluminescence intensity.
IEEE Transactions on Electron Devices | 1996
S.A. Hareland; S. Krishnamurthy; S. Jallepalli; Choh-Fei Yeap; K. Hasnat; A. Tasch; C.M. Maziar
Successful scaling of MOS device feature size requires thinner gate oxides and higher levels of channel doping in order to simultaneously satisfy the need for high drive currents and minimal short-channel effects. However, in deep submicron (/spl les/0.25 /spl mu/m gate length) technology, the combination of the extremely thin gate oxides (t/sub ox//spl les/10 nm) and high channel doping levels (/spl ges/10/sup 17/ cm/sup -3/) results in transverse electric fields at the Si/SiO/sub 2/ interface that are sufficiently large, even near threshold, to quantize electron motion perpendicular to the interface. This phenomenon is well known and begins to have an observable impact on room temperature deep submicron MOS device performance when compared to the traditional classical predictions which do not take into account these quantum mechanical effects. Thus, for accurate and efficient device simulations, these effects must be properly accounted for in todays widely used moment-based device simulators. This paper describes the development and implementation into PISCES of a new computationally efficient three-subband model that predicts both the quantum mechanical effects in electron inversion layers and the electron distribution within the inversion layer. In addition, a model recently proposed by van Dort et al. (1994) has been implemented in PISCES. By comparison with self-consistent calculations and previously published experimental data, these two different approaches for modeling the electron inversion layer quantization are shown to be adequate in order to both accurately and efficiently simulate many of the effects of quantization on the electrical characteristics of N-channel MOS transistors.
Solid-state Electronics | 1991
H. Shin; G.M. Yeric; A. Tasch; C.M. Maziar
Abstract A new physically-based semi-empirical equation for electron effective mobility in MOS inversion layers has been developed by accounting explicitly for surface roughness scattering and screened Coulomb scattering in addition to phonon scattering. The new semi-empirical model shows excellent agreement with experimentally measured effective mobility data from five different published sources for a wide range of effective transverse field, channel doping, fixed interface charge, longitudinal field and temperature. By accounting for screened Coulomb scattering due to doping impurities in the channel, our model describes very well the roll-off of effective mobility in the low field (threshold) region for a wide range of channel doping level ( N A = 3.9 × 10 15 −7.7 × 10 17 cm −3 ). We have also developed a local-field-dependent mobility model for electrons in the inversion layer for use in device simulators by applying the previously published method to this new semi-empirical equation for the effective mobility. The new local-field-dependent mobility model has been implemented in the PISCES 2-D device simulation program, and comparisons of calculated vs measured data show excellent agreement for I D − V G and I D − V D curves for different devices with L eff ranging from 0.5 to 1.2 μ.
IEEE Transactions on Ultrasonics Ferroelectrics and Frequency Control | 1991
John Carrano; C. Sudhama; Vinay Chikarmane; Jack C. Lee; A. Tasch; William H. Shepherd; Norman E. Abt
The electrical and reliability characteristics of ferroelectric capacitors fabricated using sol-gel derived 50/50 lead-zirconate-titanate (PZT) thin films have been examined for ULSI DRAM (dynamic random access memory) applications. Various electrode materials, film thicknesses (200 nm to 600 nm) and capacitor areas were used. A large stored-energy density (Q/sub c/) of 15 mu C/cm/sup 2/ (at 125 kV/cm) was measured using different methods. The results indicate that PZT thin films exhibit material properties which might satisfy the requirements of ULSI DRAMs.<<ETX>>
Applied Physics Letters | 1989
L. Breaux; B. Anthony; T. Hsu; Sanjay K. Banerjee; A. Tasch
Low‐temperature silicon epitaxy is critical for future generation ultralarge scale integrated circuits and silicon‐based heterostructures. Remote plasma‐enhanced chemical vapor deposition has been applied to achieve silicon homoepitaxy at temperatures as low as 150 °C, which is believed to be the lowest temperature reported to date. Critical to the process are an in situ remote plasma hydrogen cleaning of the substrate surface in an ultrahigh vacuum growth chamber prior to epitaxy, and substitution of thermal energy by remote plasma excitation via argon metastables and energetic electrons to dissociate silane and increase adatom mobility on the surface of the silicon substrate. Excellent crystallinity with very few defects such as dislocations and stacking faults is observed.
IEEE Electron Device Letters | 1997
G. Chindalore; S.A. Hareland; S.A. Jallepalli; A. Tasch; C.M. Maziar; V.K.F. Chia; S. Smith
The authors report for the first time, accurately extracted experimental data for the threshold voltage shift (/spl Delta/V/sub T/) due to quantum mechanical (QM) effects in hole inversion layers in MOS devices, Additional experimental results are presented for QM effects in electron inversion layers. Compared to classical calculations, which ignore QM effects, these effects are found to cause a significant increase in the threshold voltage (/spl sim/100 mV) in MOSFET devices with oxide thicknesses and doping levels anticipated for technologies with gate lengths /spl les/0.25 /spl mu/m. /spl Delta/V/sub T/ has been determined from experimental devices with doping levels ranging from 5/spl times/10/sup 15/-1/spl times/10/sup 18//cm/sup 3/, and recently developed theoretical models are found to agree well with the results. In addition, an innovative technique using a two-dimensional (2-D) device simulator in conjunction with the experimental capacitance-voltage (C-V) characteristics has been developed in order to more accurately extract various physical parameters of the MOS structure.
IEEE Transactions on Electron Devices | 1989
Hyungsoon Shin; A. Tasch; C.M. Maziar; Sanjay K. Banerjee
A modeling approach is described that extracts the functional dependence of carrier mobility on local transverse and longitudinal fields, channel doping, fixed interface charge, and temperature in MOS inversion and accumulation layers directly from the experimentally measured effective (or average) mobility. This approach does not require a priori detailed knowledge of the experimental variation of mobility within the inversion or accumulation layer, and it can be used to evaluate the validity of other models described in the literature. Also, an improved transverse-field dependent mobility model is presented for electrons in MOS inversion layers that was developed using this new modeling approach. This model has been implemented in the PISCES 2-D device simulation program. Comparisons of the calculated versus measured data show excellent agreement for I/sub D/-V/sub G/ and I/sub D/-V/sub D/ curves for devices with L/sub eff/=0.5 to 1.2 mu m. >
IEEE Transactions on Electron Devices | 1992
Kevin M. Klein; Changhae Park; A. Tasch
An improved Monte Carlo simulation model has been developed for boron implantation into single-crystal silicon. This model is based on the Marlowe Monte Carlo code and contains significant improvements for the modeling of ion implantation, including a newly developed local electron concentration-dependent electronic stopping model and a newly developed cumulative damage model. These improvements allow the model to reliably predict boron implant profiles not only as a function of energy, but also as a function of other important implant parameters such as tilt angle, rotation angle, and dose. In addition, profiles of implant generated point defects (silicon interstitials and vacancies) can be calculated. >
IEEE Transactions on Electron Devices | 1996
K. Hasnat; Choh-Fei Yeap; S. Jallepalli; W.-K. Shih; S.A. Hareland; V.M. Agostinelli; A. Tasch; C.M. Maziar
An energy parameterized pseudo-lucky electron model for simulation of gate current in submicron MOSFETs is presented in this paper. The model uses hydrodynamic equations to describe more correctly the carrier energy dependence of the gate injection phenomenon. The proposed model is based on the exponential form of the conventional lucky electron gate current model. Unlike the conventional lucky electron model, which is based on the local electric fields in the device, the proposed model accounts for nonlocal effects resulting from the large variations in the electric field in submicron MOSFETs. This is achieved by formulating the lucky electron model in terms of an effective-electric field that is obtained by using the computed average carrier energy in the device and the energy versus field relation obtained from uniform-field Monte Carlo simulations. Good agreement with gate currents over a wide range of bias conditions for three sets of devices is demonstrated.
IEEE Electron Device Letters | 2001
Sivakumar Mudanai; Leonard F. Register; A. Tasch; Sanjay K. Banerjee
A comprehensive analysis of the effects of wave function penetration on the capacitance of NMOS capacitors has been performed for the first time, using a self-consistent Schrodinger-Poisson solver. The study reveals that accounting for wave function penetration into the gate dielectric causes carrier profile to be shifted closer to the gate dielectric reducing the electrical oxide thickness. This shift increases with increasing gate voltage. For example, in one simulation, the peak is shifted by about 0.2 nm at a surface field of 1.96 MV/cm and 0.33 nm at a surface field of 3.7 MV/cm. This shifting results in all increased capacitance. The increase in capacitance observed in the inversion region is relatively insignificant when a poly gate electrode with a doping of less than 1/spl times/10/sup 20/ cm/sup -3/ is used due to the poly-depletion effect. A physical picture of the effect of physical thickness on the tunneling current is also presented.