Aalap Tripathy

Representation of Complex Concepts for Semantic Routed Network

Semantic Routed Network (SRN) can provide a scalable distributed solution for searching data in a large grid. In SRN, messages are routed in a overlay network based on the meaning of the message key. If the message key describes the desired data, then SRN nodes can be addressed and accessed by the description of their data content. The key challenges of materializing a SRN are: (1) designing a data structure which will represent complex descriptions of data objects; (2) computing similarity of descriptors; and (3) constructing a small world network topology that minimize the routing response time and maximize routing success, which depends on solving the first two problems. We present a design of a descriptor data structure and a technique to compare their similarity to address the first two problems.

Designing a Collaborative Filtering Recommender on the Single Chip Cloud Computer

Fast response requirements for big-data applications on cloud infrastructures continues to grow. At the same time, many cores on-chip have now become a reality. These developments are set to redefine infrastructure nodes of cloud data centers in the future. For this to happen, parallel programming runtimes need to be designed for many-cores on chip as the target architecture. In this paper, we show that the commonly used MapReduce programming paradigm can be adapted to run on Intels experimental single chip cloud computer (SCC) with 48-cores on chip. We demonstrate this using a Collaborative Filtering (CF) recommender system as an application. This is a widely used technique for information filtering to predict users preference towards an unknown item from their past ratings. These systems are typically deployed in distributed clusters and operate on large apriori datasets. We address scalability with data partitioning, combining and sorting algorithms, maximize data locality to minimize communication cost within the SCC cores. We demonstrate ~2x speedup, ~94% lower energy consumption for benchmark workloads as compared to a distributed cluster of single and multi-processor nodes.

A parallel architecture for meaning comparison

In this paper we present a fine grained parallel architecture that performs meaning comparison using vector cosine similarity (dot product). Meaning comparison assigns a similarity value to two objects (e.g. text documents) based on how similar their meanings (represented as two vectors) are to each other. The novelty of our design is the fine grained parallelism which is not exploited in available hardware based dot product processor designs and can not be achieved in traditional server class processors like the Intel Xeon. We compare the performance of our design against that of available hardware based dot product processors as well a server class processor using optimum software code performing the same computation. We show that our hardware design can achieve a speedup of 62,000 times compared to an available hardware design and a speedup of 8866 times with 33% (1.5 times) less power consumption, compared to software code running on Intel Xeon processor for 1024 basis vectors. Our design can significantly reduce the amount of servers required for similarity comparison in a distributed search engine. Thus it can enable reduction in energy consumption, investment, operational costs and floor area in search engine data centers. This design can also be deployed for other applications which require fast dot product computation.

A reconfigurable computing architecture for semantic information filtering

The increasing amount of information accessible to a user digitally makes information retrieval & filtering difficult, time consuming and ineffective. New meaning representation techniques proposed in literature help to improve accuracy but increase problem size exponentially. In this paper, we present a novel reconfigurable computing architecture that addresses this issue, outperforms contemporary many-core processors such as Intels Single Chip Cloud computer and Nvidias GPUs by ~20x for semantic information filtering. We validate our design using industry standard System-on-chip virtual prototyping and synthesis tools. Such a high performance reconfigurable architecture can form a template for a wide range of content-based and collaborative filtering engines used for big-data analytics.

Parallel Processor Core for Semantic Search Engines

Superior and fast semantic comparison improves the quality of web-search. Semantic comparison involves dot product computation of large sparse tensors which is time consuming and expensive. In this paper we present a low power parallel architecture that consumes only 15.41 Watts and demonstrates a speed-up in the order of 10textsuperscript{5} compared to a contemporary hardware design, and in the order of 10textsuperscript{4} compared to a purely software approach. Such high performance low power architecture can be used in semantic routers to elegantly implement energy efficient distributed search engines.

Distributed Collaborative Filtering on a Single Chip Cloud Computer

Many-cores on chip have now become a reality. They necessitate the revisit of several layers of a cloud infrastructure. For this to happen, parallel programming runtimes need to be designed for many-cores on chip as the target architecture. In this paper, we show that Map Reduce programming paradigm can be adapted to run on Intels experimental single chip cloud computer (SCC) with 48-cores on chip. We demonstrate this using a Collaborative Filtering (CF) recommender system as an application. CF is widely used in e-commerce deployments to predict users preference towards an unknown item from their past ratings. We address scalability with data partitioning, combining and sorting algorithms, maximize data locality to minimize communication cost within the SCC cores. We demonstrate ~2x speedup, ~94% lower power consumption for benchmark workloads as compared to a distributed cluster multi-processor nodes in use today.