Aaron J. Goldberg

Interrupt-based hardware support for profiling memory system performance

Fueled by higher clock rates and superscalar technologies, growth in processor speed continues to outpace improvement in memory system performance. Reflecting this trend, architects are developing increasingly complex memory hierarchies to mask the speed gap, compiler writers are adding locality enhancing transformations to better utilize complex memory hierarchies, and applications programmers are recoding their algorithms to exploit memory systems. All of these groups need empirical data on memory system behavior to guide their optimizations. This paper describes how to combine simple hardware support and sampling techniques to obtain such data without appreciably perturbing system performance. The idea is implemented in the Mprof prototype that profiles data stall cycles, first level cache misses, and second level misses on the Sun Sparc 10/41.

Mtool: an integrated system for performance debugging shared memory multiprocessor applications

The authors describe Mtool, a software tool for analyzing performance losses in shared memory parallel programs. Mtool augments a program with low overhead instrumentation which perturbs the programs execution as little as possible while generating enough information to isolate memory and synchronization bottlenecks. After running the instrumented version of the parallel program, the programmer can use Mtools window-based user interface to view compute time, memory, and synchronization objects. The authors describe Mtools low overhead instrumentation methods, memory bottleneck detection technique, and attention focusing mechanisms, contrast Mtool with other approaches, and offer a case study to demonstrate its effectiveness. >

Performance debugging shared memory multiprocessor programs with MTOOL

No abstract available

Architectural support for performance tuning: a case study on the SPARCcenter 2000

Latency hiding techniques such as multilevel cache hierarchies yield high performance when applications map well onto hierarchy implementations, but performance can suffer drastically when they do not. Identifying and reducing mismatches between an application and the memory hierarchy is difficult without insight into the actual behavior of the hardware implementation. We advocate the use of hardware event counters, as a cheap, effective and practical way to tune applications for a given hardware platform. We take a case study approach, focussing on the counters available on the SPARCcenter 2000, a 20 processor, shared-bus based multiprocessor. We describe the tools we built to relate hardware event counts to user applications and give examples to illustrate how these tools are useful in practice. We conclude with a critique of the current hardware counters, offering a users perspective on how they could be redesigned to be more effective.

MTOOL: a method for detecting memory bottlenecks

This paper presents a new, relatively inexpensive method for detecting regions (e.g. loops and procedures) in a program where the memory hierarchy is performing poorly. By observing where actual measured execution time differs from the time predicted given a perfect memory system, we can isolate memory bottlenecks. MTOOL, an implementation of the approach aimed at applications programs running on MIPS-chip based workstations is described and results for some of the Perfect Club and SPEC benchmarks are summarized.

Scalable and non-intrusive load sharing in owner-based distributed systems

Previously proposed load sharing algorithms do not support flexible sharing policies in a non-intrusive fashion and do not scale to systems consisting of several thousand workstations, and, therefore, are not amenable for owner-based distributed systems. The paper introduces a new algorithm that supports a rich set of policies while scaling to adequate system sizes with bounded intrusiveness.<<ETX>>

Virtual computers-a new paradigm for distributed operating systems

The virtual computers (VC) paradigm enables the incorporation of predictability and choice into the design of an operating system. Predictability refers to the ability of the system to provide each user with a computing environment whose performance is independent of the behavior of other users. Choice refers to the ability of a user to select a computer system that meets that users specifications, needs or budget. In this paper, we introduce this new paradigm and show how the VC paradigm can be incorporated into the processor scheduling, and how the on-line schedulers can be effectively implemented.<<ETX>>