Abdoul Rjoub

Low-power/low-swing domino CMOS logic

A new low-power domino CMOS logic is introduced. Its power characteristics are based on a low voltage swing technique. The output inverter of the domino gate is modified in order to reduce its output voltage swing. This results in dynamic power dissipation saving up to 36% and improvement in the power-delay product. A technique for creating changeable values of the voltage swing is used achieving various trade-off between power savings and speed. Experimental results clearly show the validity of the proposed technique for low-power operation.

Efficient multi-threshold voltage techniques for minimum leakage current in nanoscale technology

The influence of multi-threshold voltage technique on reducing the leakage power in CMOS circuits at transistor level based on Nanoscale SPICE parameters is investigated in this paper. Based on Artificial Intelligence search algorithms, three new algorithms are proposed to determine the exact threshold voltage for each transistor in order to minimize the leakage current at lowest value. These algorithms are: Slack Time Search Algorithm (STS), Leakage Power Search Algorithm (LPS), Leakage and Slack Time Search Algorithm (LSS). As a result, 70% of sub-threshold leakage current is reduced without degrading the performance. Based on 22 nm predictive SPICE parameters proposed by BSIM4, simulation results verified the validity of the proposed algorithms. Copyright

A Fast Input Vector Control approach for Sub-threshold leakage power reduction

Due to the significance of leakage power for CMOS circuits at Nanoscale, a new technique for Sub-threshold leakage current reduction based on Input vector control (IVC) is proposed. The proposed algorithm is called Fast Input Vector Algorithm (FIVA). It is characterized as faster than other algorithms, its speed doubles strongly of other algorithms speed when the number of circuit inputs increases. Simulation results show that the efficiency of the proposed algorithm increases by increasing the number of input vector. For 2-bits Full Adder, FIVA has speed up reaches 70%. For 8-bits Full Adder, FIVA has speed up reaches 97%, which validates the proposed algorithm.

Low voltage swing gates for low power consumption

A low swing voltage design technique is proposed. The new design could be used successfully in order to decrease the power dissipation in Complementary Pass-Transistor Logic (CPL) as in Cascade Voltage Switch Logic (CVSL) logic gates. The achieved gate output voltage-level swing reduction, results in a significant reduction of their power consumption. Using the proposed technique, for supply voltage 3.3 V and 0.5 /spl mu/m CMOS process technology, 35% (for the CPL) and 20% (for the CVSL) power consumption savings is achieved. Improvements in power-delay product are also obtained. In the new gates no special circuit design receiver is required in order to pull-up the low swing signal.

An efficient low-power bus architecture

In this paper a new low power bus architecture based on the reduced voltage swing technique, is proposed. A driver circuit and a receiver are designed using strictly simple design principles and conventional CMOS technology. A considerable reduction in power consumption is achieved. The influence of the swing level on the time performance is also examined. The same architecture with a new repeater circuit is used, for driving internal long interconnection lines and similar results are obtained.

Drain induced barrier lowering (DIBL) accurate model for nanoscale Si-MOSFET transistor

In this paper, an accurate new model for drain induced barrier lowering (DIBL) tunneling in silicon on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) is proposed. The effect of drain (Vds) and substrate (Vbs) voltages variation on DIBL is discussed. The dependency of channel length variation (ΔL), junction depth (rj), and substrate impurity concentration (NB) on DIBL is analyzed, and new equations are obtained. The evaluation results for the proposed model using MATHEMATICA give good agreement when compared with analytical and simulation results for BSIM4 level 54 and recent well-known models using HSPICE simulator.

Low power/high speed optimization approaches of MISTY algorithm

This paper presents two approaches targeting the reduction of power dissipation, the delay time and silicon area of S7 and S9 blocks of MISTY1 encryption algorithm. The essential part of both approaches is to reduce the number of logic gates (XOR and AND gates) used in S7 and S9 blocks ciphers. The first approach reduces the number of logic gates by applying Boolean Algebra rules and simplifications, while the second approach removes the redundant logic gates which form the S7 and S9 blocks ciphers. The first approach reduced the dynamic power dissipation and the silicon area by 21.7%, 25.3%, respectively, while the throughput enhanced by 21.1%. The second approach reduced the dynamic power dissipation and the silicon area by 27%, 31.7%, respectively, while the throughput enhanced by 3.8%. As a result, the proposed approaches could be fit for next generation of handheld and portable devices.

Carbon nanotube field effect transistor models performance and evaluation

This paper presents a comparison between different models that have studied the effects of several parameter scaling on the performance of Carbon Nano Tube Field Effect Transistors. This evaluation for the studied models, with regard to the scaling effects, is to determine those which best reflect the very essence of Carbon Nano Tubes. Whereas the models subject this comparison (Fettoy, Roy, Stanford, and Southampton) are affected to varying degrees due to such parametric variations, the Stanford model is shown as still being valid for a wide range of chirality and diameters; a model that is also applicable for circuit simulations. Simulations show that the Southampton model was more realistic considering the non-ideality of the carbon nanotube, also with less computational efforts. Results leveraging our findings in this ongoing research endeavor reveal that many research efforts were not efficient to high degree due to high delay and not valid for circuit simulations.

Multithreshold voltage low-swing/low-voltage techniques in logic gates

A low-power design circuit using low-swing voltage technique is proposed in this paper. The proposed technique could be used in order to decrease the power dissipation in three different types of logic gates namely the complementary pass-transistor logic (CPL), the cascade voltage switch logic (CVSL), and the domino logic. The main idea of the proposed technique is based on the replacement of the conventional CMOS inverter at the output of the logic gates with a new low-swing voltage inverter based on multithreshold voltage technology (LSIM). The inserted LSIM achieves a reduction in the static power dissipation, the dynamic power dissipation as the propagation delay time of the gates. To demonstrate the impact of the proposed technique in different applications, various types of circuits are designed for different conditions of: speed operation, load capacitance and supply voltages. In order to ensure the validity of the proposed technique in large circuit designs and fanout, a 8_bit Braun multiplier is designed in the three types of logic gates. SPICE simulation results for 3.3 V supply voltage using 0.5 µm multithreshold technology prove that 32%, 30% and 34%, reduction in power dissipation and 10%, 12% and 15% reduction in delay time could be achieved for the CPL, CVSL and domino logic gates respectively.

Low-swing/low power driver architecture

A new low-swing/low-power CMOS driver architecture for VLSI applications is proposed. The architecture based on low swing technique using the conventional CMOS static logic. Simulation results based on the proposed design show significant improvements in both power dissipation and power-delay product compared to other low swing techniques driver architectures. Using 0.5 /spl mu/m CMOS technology, for 3.3 V power supply voltage, 40% lower power dissipation than the conventional CMOS bus is achieved. The influence of the swing level on the time performance is also examined.