Abdul Fatah Awang Mat

Fabrication and Characterization of PZT Thin Film Capacitors for MMIC Applications

This paper reports on the use of thin lead zirconate titanate (PZT) films for monolithic microwave integrated circuit (MMIC) capacitors to replace existing materials for better size-reduction. The films were sputtered on Pt/Ti/SiO2 coated, undoped silicon wafers. Square Pt electrodes with sides ranging from 10 mum to 50 mum were patterned on the PZT layers to form the capacitors. Results of this study show that PZT thin films can be utilized for efficient size reduction in MMIC. The linewidth obtained for a 50 Omega transmission line is merely 300 nm - this results in a size reduction of approximately five times compared to conventional MMIC. For a 50 times 50 mum electrode area, capacitance values ranging from 5 to 20 pF were obtained at frequencies up to 20 GHz. Suitable de-embedding of S parameters using Cascade microwave probes revealed films with relative permittivities of the order of 100 to 500

The microstrip coupled line Bandpass filter using LTCC technology for 5GHz wireless LAN application

This paper presents a top-down design of the microstrip coupled line Band pass filter (BPF) embedded in low temperature co-fired ceramic (LTCC) for 5 GHz wireless LAN applications. It includes the design, simulation, fabrication and measurements. The filter circuit was designed and simulated based on Agilent Advanced Automation (ADS2005A) software. Then, the physical dimensions of components and the filter itself is subsequently determined and the physical design is later performed in the layout window of Empire XcCEL. All measured simulations are analyzed and compared to design specifications and characteristics (curve fitting). Any inaccuracy is taken into account where corrected design is further recovered.

An LTCC design technique based on FDTD EM simulations

This paper described the Low Technology Co-fired Ceramic (LTCC) design methodology at TMRND based on FDTD EM simulations that are required when designing the RF/microwave circuit. In this paper, 3D EM analysis and optimization with Finite Different Time Domain (FDTD) software Empire XcCeltrade from IMST was applied to achieve accurate modeling of the RF/microwave circuit using LTCC technology. A multilayer spiral inductor was selected for discussion to show this LTCC design technique. The main elements of the LTCC design technique relies on three important guidelines; use accurate component models, link the circuit schematic to the layout to reduce errors and finally link the layout to an EM simulator to detect coupling problems.

Designing 5GHz microstrip coupled line bandpass filter using LTCC technology

A top-down detail design of a 5 GHz micro strip coupled line band pass filter in LTCC is presented in this paper. LTCC, which stands for low temperature co-fired ceramic is especially used for wireless and high-frequency applications. Now, the importance of LTCC is becoming more prominent in views of the fact a lot organizations has been funding R&D-projects regarding this new technology that focuses on larger implementation of functionality in LTCC substrates. Although Malaysia is new to this technology, its industry has certainly high hopes on the LTCC innovation to make a breakthrough and contribute significant benefits to the technology, industry, market and also, the country itself. The filter circuit was designed and simulated by using ADS2005A. Then, the physical dimensions of components and the filter itself is subsequently determined and the physical design is later performed in the layout window of Empire XcCEL. All measured simulations are analyzed and compared to design specifications and characteristics (curve fitting). Any inaccuracy is taken into account where corrected design is further recovered.

Design of 2-stage medium power amplifier using 0.5 μm GaAs PHEMT for wireless LAN applications

This paper presents the design and fabrication of two-stage medium power amplifier (MPA) using 0.5 mum GaAs PHEMT technology for the wireless LAN applications. The die size of this amplifier is only 1.7 mm times 0.85 mm. At a supply voltage of 5.0 V and 5.8 GHz operating frequency, a 2-stage MPA achieves a linear gain (S21) of 16.39 dB, P1 dB of 20.18 dBm, power gain of 15.15 dB and the PAE of 25.29%.

Parasitic effects of spiral inductors on the performance of GaAs-based MMIC low noise amplifier

This paper is discusses about parasitic effect of spiral inductors on 5.8 GHz low noise amplifier (LNA) performances based on 0.5 mum GaAs pHEMT technology. Using S-parameter simulation, performance of the LNA between lump and distributed circuit are compared at 5.8 GHz. Electrical performance of the LNA performances by placing ideal components with non-ideal components shows that noise figure is increased by 2.31 dB, gain is decreased by 11.38 dB and input and output return loss is increased by 0.31 dB and 4.31 dB respectively. By using non-ideal components in the lump circuit analysis, it is shown that the spiral inductor has a noticeable impact on the LNA performance. The parasitic effects including self resonance on spiral inductors is discussed. This analysis is essential to ensure the simulation results yield realistic measured results for the fabricated LNA. Therefore the designer will have a good estimation on the performance of the LNA performance during the design stage prior to the testing stage.

A wide gain-bandwidth CMOS fully-differential folded cascode amplifier

This paper presents a CMOS fully differential folded cascode that operates at high frequency. Theoretical study on this amplifier is first presented and analyzed. The crucial parameters that may have influences on the trade-off for the design of this amplifier are also presented. Simulation results showing the characteristics of this amplifier are discussed. Using technology CMOS 0.18µm with power supply equals to 3.3V, this amplifier results a gain of 63.12dB, a unity-gain bandwidth of 1.99GHz, a phase margin of 56.9° and it consumes a total current of 1.15mA.

Gain and cut-off frequency analysis of multiple-gated AlGaAs/InGaAs HEMTs

A small signal analysis was performed on a specific 0.2 mum HEMT device to study the impact of multiple-gated layout towards the gain and cut-off frequency performance. The characterization process was using on-wafer measurement technique to AlGaAs/InGaAs HEMT devices which consisted of three types of layouts of various gate finger numbers and widths. The devices were biased at the optimum basing voltage obtained from DC characterization performed previously. From the result, it was observed that the device with higher number of gates exhibited higher gain only at low frequency, while at higher frequency the gain dropped significantly. This significant drop in gain was due to the increase of the gate-source capacitance in the device, thus leading to a reduction of the device cut-off frequency. The experimental findings were strongly supported by simulation which was based on related theory on the layout dimension contribution.

The Impact of Multiple-Gated Layout on the Drain-Source Current of pseudomorphic-HEMTS

The measurement and analysis to search the impact of multiple-gated structure of a GaAs based p-HEMT device towards the drain-source current (Ids) is presented here. The experimental works had been carried out on the GaAs wafer that consists of 2times60, 4times75 and 6times150 p-HEMT device layouts for the I-V characteristic. The I-V measurement was performed using on-wafer probing technique which applied semi-auto probe station and Keithley parameter analyzer to extract I-V curve. From the I-V data, it was found that the p-HEMT layout that had higher number of gates exhibited a significant impact on the Ids at the same Vgs bias value. The Ids of six-gated layout was improved about 40% as compared to 4-gated layout and about 60% to 2-gated layout. The effect on the I-V performance due to the number of gates in the layout has also been discussed in detail for circuit design applications

Development of 2.4 and 3.5 GHz 0.15 μm GaAs PHEMT medium‐power amplifier employing core‐based design approach

Purpose – The purpose of this paper is to discuss medium‐power amplifier (MPA) design using parasitic‐aware core‐based approach.Design/methodology/approach – This paper discusses a core‐based design approach, which can also deliver multi‐band radio frequency integrated circuit.Findings – A fabricated 3.5 GHz MPA achieved a P1dB of 16.81 dBm, power‐added efficiency (PAE) of 16.74 percent and gain of 6.81 dB at the 10 dBm of input power under a low‐power supply of 3 V. The maximum current, Imax is 80.7 mA and the power consumption of the device is 242.10 mW. A fabricated 2.4 GHz MPA achieved a P1dB of 14.83 dBm, PAE of 11.73 percent and gain of 9.83 dB at the 5.0 dBm of input power under a low‐power supply of 3.0 V. The maximum current, Imax is 84.4 mA and the power consumption for this device is 253.20 mW.Originality/value – This paper shows the merits of the parasitic‐aware design methods used in designing the core circuit.