Abhaya Asthana

An Indoor Wireless System for Personalized Shopping Assistance

By integrating wireless, video, speech and real-time data access technologies, a unique shopping assistant service can be created that personalizes the attention provided to a custorner based on individual needs, without limiting his movement, or causing distractions from others in the shopping center. We have developed this idea into a service based on two products: a very high volume hand-held wireless communications device. the PSA (Personal Shopping Assistant), that the customer owns (or rnay be provided to a customer by the retailer), and a centralized server located in the shopping center to which the custorner communicates using the PSA. The centralized server maintains the customer database. the store database and provides audio/visual responses to inquiries fronr tens to hundreds of customers in real-time over a snrull areo wrteless network.

A small domain communications system for personalized shopping assistance

By integrating wireless, video, speech and real-time data access technologies, a unique shopping assistant service can be created that personalizes the attention provided to a customer based on individual needs, without limiting his movement, or causing distractions for others in the shopping center. We have developed this idea into a service based on two products: a very high volume hand-held wireless communications device, the PSA (Personal Shopping Assistant), that the customer owns (or may be provided to a customer by the retailer), and a centralized server located in the shopping center to which the customer communicates using the PSA. The centralized server maintains the customer database, the store database and provides audio/visual responses to inquiries from tens of customers in real-time over a small area wireless network.

Towards a Gigabit IP Router

In this paper we illustrate the application of SWIMs Active Storage Element (ASE) module in constructing high performance IP routers. The logic associated with each ASE is a wide-instruction-word micro-programmable engine, that has been specially designed to efficiently perform operations such as pointer dereferencing, memory indirection, bounds checking, and so forth. This makes it well suited to performing operations such as parsing of the IP header, routing table lookup, checksum computation and exception processing. Our results show that a single ASE running at 20 MHz can process 400,000 packets per second: well over that required to sustain a gigabit router. Multiple ASEs can be used in parallel to achieve even higher processing rates.

A testbed for mobile networked computing

The rapid deployment of wireless access technology, along with the emergence of high speed integrated service networks, promises to provide users with ubiquitous access to multimedia information in the near future. We are building an experimental testbed system, SWAN (Seamless Wireless ATM Network), to mimic this emerging networking environment. Our wireless access network is organized according to a nanocellular design with base stations serving as a gateway for communication between the wired network and the mobile hosts in a cell. Normally, a mobile host sends and receives traffic through the base station in its current cell. But SWAN also supports direct ephemeral networking between a limited number of cooperating mobile hosts within a small domain. The heart of the testbed is a networking subsystem, FAWN (Flexible Adapter for Wireless Networking) that interfaces the standard PCMCIA bus to an RF modem. The FAWN interface is used with a PC or workstation connected to a wired backbone network or a portable device such as a laptop or palmtop computer. In addition, a user interface consisting of an LCD display, audio I/O, and a bar code reader has been built. When interfaced with FAWN this results in a portable wireless multimedia terminal.

Quantifying software reliability and readiness

As the industry moves to more mature software processes (e.g., CMMI) there is increased need to adopt more rigorous, sophisticated (i.e., quantitative) metrics. While quantitative product readiness criteria are often used for business cases and related areas, software readiness is often assessed more subjectively & qualitatively. Quite often there is no explicit linkage to original performance and reliability requirements for the software. The criteria are primarily process-oriented (versus product oriented) and/or subjective. Such an approach to deciding software readiness increases the risk of poor field performance and unhappy customers. Unfortunately, creating meaningful and useful quantitative in-process metrics for software development has been notoriously difficult.

Design of an active memory system for network applications

We describe an active memory named SWIM (Structured Wafer-based Intelligent Memory), designed for efficient storage and manipulation of data structures. The key architectural idea in SWIM is to put some processing logic inside each memory chip that allows it to perform data manipulation operations locally and to interact with a disk or a communication line through a backend port. A network or I/O subsystem is built using an interconnected ensemble of such memory logic pairs. A complex network processing task can now be distributed between a large number of small memory processors each doing a sub-task, while still retaining a transparent memory interface. We argue that active memory based processing enables more powerful, scalable and robust designs for storage and communications subsystems, that can support emerging network services, multimedia workstations and wireless PCS systems. A complete parallel hardware and software system constructed using an array of SWIM elements has been operational for over a year.<<ETX>>

An intelligent memory system

SWIM(Structured Wafer-Scale Intelligent Memory) is a high bandwidth, multi-ported, disk-sized memory system capable of storing, maintaining, and manipulating data structures within it, independent of the main processing units. Up to thousands of active storage elements, each element having some storage and some associated processing logic, function independently or in groups to implement userdefined objects. SWIM increases memory functionality to better balance the time spent in moving data with that involved in actually manipulating it. Just as one may associate a cache with each processor, each memory module has processing logic associated with it. Such logic decreases the processormemory bandwidth requirements, improves memory utilization, scales better in a multiprocessor, and yields a faster response from memory. The faster response results from proximity, a specialized micro architecture and parallelism.

Kaleido: An Integrated Architecture For Interactive Multimedia Systems

Emerging ’multimedia technologies have the potential to revolutionize the way humans organize, communicate and consume information. However, the full benefits of this technology have yet to reach the vast majority of computer users. One reason for this is that high-bandwidth networks are not widely deployed or accessibIe. But beyond the bandwidth banier, there also exists a mulfimedia compuring barrier. The architectures of present day computers are not significantly different from their earlier generation counterparts: fundamentally oriented towards &fa processing -they are simply much faster and better at it. Consequently, these systems (hardware and system software alike) are ill-equipped to cater to the special requirements imposed by multimedia. Most commonly used approach is to attach ‘multimedia’ devices such as cameras, sound-cards, CD-ROM drives as U0 peripherals to an existing computer system, and hope that a ‘fast enough’ CPU will run a few targeted applications reasonably well. It is possible, using this approach, to build some highly optimized (possibly through the use of custom hardware peripherals) stand alone multimedia applications that perfonn tolerably. However, such systems do not provide a general-purpose infra-structure to support the integration of multimedia capability into an arbitrary user application. To enable this, it is necessary to incorporate support for multimedia into the hardware and software fabric of the system, not just as ‘add-ons’. Kaleido is an experimental approach to designing such an integrated multimedia system. It is an on-going project and in this paper we present the current snap shot of our architecture and implementation.

A multi-microprocessor architecture with hardware support for communication and scheduling

We describe a multiprocessor system that attempts to enhance the system performance by incorporating into its architecture a number of key operating system concepts. In particular: — the scheduling and synchronization of concurrent activities are built in at the hardware level, — the interprocess communication functions are performed in hardware, and, — a coupling between the scheduling and communication functions is provided which allows efficient implementation of parallel systems that is precluded when the scheduling and communication functions are realized in software.

The Design of a Back-end Object Management System

We describe the architecture and design of a back-end object manager, designed as an “active memory” system on a plugin board for a standard workstation (or personal computer). We show how, with minimal modification to existing code, it is possible to achieve significant performance improvement for the execution of data-intensive methods on objects, simply by using our back-end object manager.