Abhilash J. Mayur

A Comparison of Spike, Flash, SPER and Laser Annealing for 45nm CMOS

Due to integration concerns, the use of meta-stable junction formation approaches like laser thermal annealing (LTA), solid phase epitaxial regrowth (SPER), and flash annealing has largely been avoided for the 90nm CMOS node. Instead fast-ramp spike annealing has been optimised along with co-implantation to satisfy the device requirements, often with the help from thin offset spacers. However for the 65nm and 45nm CMOS node it is widely accepted that this conventional approach will not provide the required pMOS junctions, even with changes in the transistor architecture. In this work, we will compare junction performance and integratablity of fast-ramp spike, flash, SPER and laser annealing down to 45nm CMOS. The junction depth, abruptness and resistance offered by each approach are balanced against device uniformity, deactivation and leakage. Results show that the main contenders for the 45nm CMOS are SPER and flash annealing – but both have to be rigorously optimised for regrowth rates, amorphous positioning and dopant and co-implant profiles. From the two, SPER offers the best junction abruptness ( 4E20at/cm3) and less transistor modifications. As expected, Ge and F co-implanted spike annealed junctions do not reach the 45nm node requirements. For full-melt LTA, poly deformation on isolation can be reduced but geometry effects result in unacceptable junction non-uniformity.

Ultra-low contact resistivity with highly doped Si:P contact for nMOSFET

We report a record setting low NMOS contact Rc of 2e-9 Ωcm2 with an all-silicon based solution. The ultra-low contact resistivity of Ti/Si system of 2e-9 Ωcm2 has been demonstrated with Highly Doped Si:P (HD Si:P) EPI layer which is compatible with FinFET S/D structures combined with millisecond laser anneal activation (DSA). Additionally, we show the pathway to further improve contact resistivity with HD Si:P using P implantation followed by laser anneal to reach the contact resistivity requirement for the 10nm or 7 nm nodes.

Advances on 32nm NiPt Salicide process

The two steps RTP program for 32nm NiPt silicide formation process has been evaluated to improve source-drain resistance (Rsd), resistance uniformity and device leakage reduction behavior. A lower RTP-1 process has been investigated over the Nickel rich silicide phase formation and physical defect reduction. A higher millisecond anneal (MSA) RTP-2 has been investigated of its process window on Nickel monosilicide formation without Nickel silicide agglomeration and additional nickel piping. Then the optimized RTP program which combines a lower RTP-1 and higher RTP-2 by MSA has been demonstrated effective reduction of Nickel piping by e-beam inspection count, improved source to drain resistance (Rsd) and CMOS drive current (Ion/Ioff) improvement 4% on NMOSFET and 3% on PMOSFET, respectively.

Low-Resistance Titanium Contacts and Thermally Unstable Nickel Germanide Contacts on p-Type Germanium

Ti/p-Ge and NiGe/p-Ge contacts are compared on both planar and fin-based devices. Ti/p-Ge contacts show low contact resistance, while NiGe/p-Ge devices show short circuit problems due to thermally driven Ni diffusion. Considering the thermal budget in the standard backend of line processing for CMOS, Ti is more suitable for p-Ge devices. A low Ti/p-Ge contact resistivity of 1.1 × 10-8 Ω · cm2 is achieved by using a multi-pulse laser annealing technique for B activation.

Pyrometry for laser annealing

Laser annealing is one of the process solutions to enable ultra shallow junction (USJ) formation for the 45 nm technology node. However, variations in the front-side optical properties of device wafers cause large temperature variations on the wafer surface which, in turn, cause large variations in activation of the dopants that form the junction. As a result, pyrometry and closed loop temperature control are critical to establish process uniformity and repeatability for laser annealing. Pyrometry results are presented along with the correlation between the process results (dopant activation) and the pyrometer signal. Closed loop control and future technical challenges are discussed

Ultralow-resistivity CMOS contact scheme with pre-contact amorphization plus Ti (germano-)silicidation

Following the previous study on Si:P [1], we also achieve ultralow contact resistivities (ρ_c) of ~2×10^-9 Ω·cm² on Si_0.3Ge_0.7:B using the same Ti based pre-contact amorphization (PCAI) plus post-metal anneal (PMA) technique. Similar as on Si:P, low-energy PCAI provides the lowest ρ_c on SiGe:B. By increasing the B concentration, the PMA temperature required on SiGe:B also matches with that on Si:P. A simple Ti based CMOS contact flow is thus proposed. Several B doping and activation methods on SiGe:B are also compared in this work.

Characterization of Nickel Silicides Produced by Millisecond Anneals

Nickel silicides serve as the source, drain, and gate contact material in many advanced complementary metal oxide semiconductor (CMOS) logic applications. Nickel has demonstrated numerous advantages over Cobalt and Titanium silicides of earlier technology nodes. Traditionally, these silicides have been formed by Rapid Thermal Processing (RTP) techniques. Two separate RTP anneals are typically used to form the silicides. In this paper, we explore the formation and film characteristics of nickel silicides produced by millisecond anneals. An overview is first provided of the nickel silicide resistivities as a function of RTP anneal temperature. When plotted, this data provides the transformation curves for the RTP Soak and Spike anneals of thin nickel films. A method is described for estimating the nickel silicide activation energy using these transformation curves and, subsequently, a calculation of the requisite laser power to produce a nickel silicide of comparable resistivity. Film characteristics and morphology of the resultant nickel silicides are evaluated by Transmission Electron Microscopy (TEM) and X-Ray Diffraction (XRD) analysis techniques.

Defect Evolution During Laser Annealing

Implementation of millisecond annealing requires the identification of the operating conditions for that technique which minimize the residual defects. In addition, possible combinations of low temperature annealing with millisecond annealing could result in minimal residual defects. The samples studied here were implanted with Ge+ pre-amorphization and boron dopant ions and were activated with a scanning laser annealing technique with maximum temperature dwell times of about one millisecond. The laser anneal conditions were varied, along with combinations of spike anneals. The annealed samples were analyzed by plan-view transmission electron microscopy (TEM) to measure the residual defect density and size. The effects of spike temperature, laser annealing temperature, and scan rate will be discussed.

Ultra-low NMOS contact resistivity using a novel plasma-based DSS implant and laser anneal for post 7 nm nodes

We report a record-setting low NMOS contact resistivity of 1.2×10^-9 Ωcm² compatible with Ti/Si system and dopant segregation Schottky (DSS) based solution. The ultra-low contact resistivity of Ti/Si system is demonstrated with Highly Doped Si:P Epi layer and P implantation using conformal plasma implant followed by millisecond laser anneal. Additionally, we show that short-pulse nanosecond laser as post implant anneal provides a promising pathway to further improve NMOS ρ_C to below 1×10^-9 Ωcm² for the post 7 nm nodes.

Macroscopic and nanometer scale stress measurement of Ni(Pt)Si silicide: Impact of thermal treatments ranging from millisecond to several hours

The authors have measured and compared the stress in nickel silicide full sheet layers prepared with added platinum on (001) p-type Si wafers by using either a rapid thermal anneal (RTA) at 390 °C or a millisecond submelt laser dynamic scanning anneal (DSA) at 800 °C. The room temperature tensile stress of the silicide annealed with DSA is 1.65 GPa, whereas that of the silicide annealed with RTA at 390 °C is 800 MPa. Our analysis confirms that the origin of the stress lies in thermal expansion factors. Despite some small variations, the stress remains highly tensile in both layers after a 1 h post-treatment at 400 °C, with values of 1.4 GPa and 850 MPa for the DSA and RTA samples, respectively. The authors also performed strain measurements with dark field electron holography in the source drain region of 28 nm field complementary metal oxide semiconductor field effect transistors, under the silicide dot. They then determined the stress inside the silicide by combining the strain measurement with finite element mechanical simulations; values of 1.5 GPa and 600 MPa were found at the nanometer scale for the DSA and RTA samples, respectively, which are consistent with the macroscopic observations.