Abhishek Misra

Work function modulation and thermal stability of reduced graphene oxide gate electrodes in MOS devices.

Work function (WF) tuning of the contact electrodes is a key requirement in several device technologies, including organic photovoltaics (OPVs), organic light-emitting diodes (OLEDs), and complementary metal oxide semiconductor (CMOS) transistors. Here, we demonstrate that the WF of the gate electrode in an MOS structure can be modulated from 4.35 eV (n-type metal) to 5.28 eV (p-type metal) by sandwiching different thicknesses of reduced graphene oxide (rGO) layers between top contact metals and gate dielectric SiO2. The WF of the gate electrode shows strong dependence on the rGO thickness and is seen to be nearly independent of the contact metals used. The observed WF modulation is attributed to the different amounts of oxygen concentrations in different thicknesses of rGO layers. Importantly, this oxygen concentration can also be varied by the reduction extent of the graphene oxide as experimentally demonstrated. The results are verified by X-ray photoelectron spectroscopy and Fourier transform infrared spectroscopy analyses. The obtained WF values are thermally stable up to 800 °C. At further high temperatures, diffusion of metal through the rGO sheets is the main cause for WF instability, as confirmed by cross-sectional high-resolution transmission electron microscopy analysis. These findings are not limited to MOS devices, and the WF modulation technique has the potential for applications in other technologies such as OLEDs and OPVs involving graphene as conducting electrodes.

Work function tuning and improved gate dielectric reliability with multilayer graphene as a gate electrode for metal oxide semiconductor field effect device applications

Graphene with varying number of layers is explored as metal gate electrode in metal oxide semiconductor structure by inserting it between the dielectric (SiO2) and contact metal (TiN) and results are compared with TiN gate electrode. We demonstrate an effective work function tuning of gate electrode upto 0.5 eV by varying the number of graphene layers. Inclusion of even 1-3 layers of graphene results in significantly improved dielectric reliability as measured by breakdown characteristics, charge to breakdown, and interface state density. These improvements are attributed to the impermeability of graphene for TiN and hence reduced metallic contamination in the dielectric.

Multilayer Graphene as Charge Storage Layer in Floating Gate Flash Memory

Charge storage capability of multilayer graphene (MLG) in floating gate flash memory structure is demonstrated. MLG sheets are considered for this purpose because of the higher work function and higher density of states compared to single layer graphene (SLG) and lower conductivity along c-axis. A memory window of 6.8V for 1 second programming is obtained at ±18V program/erase voltage. Number of electrons stored in MLG sheets after 18V programming voltage is calculated as 9.1 × 1012 cm-2 which is higher than the density of states in SLG, suggesting the suitability of MLG for multi level data storage flash memory devices.

Aluminum Oxide Deposited by Pulsed-DC Reactive Sputtering for Crystalline Silicon Surface Passivation

In this paper, we report on the surface passivation of crystalline silicon (c-Si) by pulsed-dc (p-dc) reactive-sputtered aluminum oxide (AlO<i>x</i>) films. For the activation of surface passivation, the films were subjected to post deposition annealing (PDA) in different ambients namely N₂, N₂ + O₂, and forming gas (FG) in the temperature range of 420-520°C. The surface passivation was quantified by surface recombination velocity, which was correlated to the interface states at the silicon-dielectric interface and fixed charges in the dielectric. A good quality surface passivation with effective surface recombination velocity <i>S</i>_eff of 41 cm · s^-1 is obtained for PDA in N₂ or N₂ + O₂ gas ambient. PDA in FG ambient at high temperature is found to degrade the passivation. The AlO_x film annealed in FG ambient shows poorer thermal stability as compared with films annealed in the other two ambients. A clear path for further improvements in surface passivation quality of p-dc reactive sputter-deposited AlO<i>x</i> is suggested based on cross-sectional transmission electron microscopy and X-ray photoelectron spectroscopy analysis and electrical data.

Enhanced Ge n + /p Junction Performance Using Cryogenic Phosphorus Implantation

In this paper, we present a detailed study of temperature-based ion implantation of phosphorus dopants in Ge for varying dose and anneal conditions through fabricated n+/p junctions and n-type MOSFETs (nMOSFETs). In comparison with room temperature (RT) (25 °C) and hot (400 °C) implantation, cryogenic (-100 °C) implantation with a dose of 2.2e15 cm-2 followed by a (400 °C) rapid thermal annealing leads to 1) lower junction leakage with higher activation energy and 2) lower sheet resistance with higher dopant activation and shallower junction depth. Gate-last Ge nMOSFETs fabricated using cryogenic implanted n+/p source/drain junction (2.2e15 cm-2) exhibit lower OFF-current (upto 5x) and higher ON-current compared with RT (25 °C) and hot (400 °C) implanted nMOSFETs. This paper demonstrates that cryogenic implantation (-100 °C) can enable high-performance Ge nMOSFETs by alleviating the problems of lower activation and high diffusion of phosphorus in Ge.

Effect of top metal contact on electrical transport through individual multiwalled carbon nanotubes

The effect of position of top metal contact on the electrical transport through individual multiwalled carbon nanotubes (MWNTs) has been investigated using gas injection system in situ in scanning electron microscope to deposit the top platinum metal contacts at different desired sites on the side contacted MWNTs in bridging structure. Current-voltage measurements reveal a significant improvement in electrical properties of the tubes after the top contact is made. This improvement has been found to be independent of position of top contact, i.e., whether the top contact is made on the ends or at any other site of the tube.

Electrical transport and breakdown in graphene multilayers loaded with electron beam induced deposited platinum.

We demonstrate here the effect of electron beam induced deposited platinum on the electrical transport through multilayer graphene sheets. Platinum metal is deposited at different positions on the graphene multilayers, i.e., including as well as excluding the bottom contact sites and the change in electrical conductance of the same multilayer graphene sheets before and after platinum deposition is segregated. An improvement in electrical conductance is observed even if the metal is deposited at the part of the graphene sheets that does not touch the bottom gold electrodes, and hence this experimental approach directly demonstrates that the contact improvement is not the sole reason for the improved electrical conduction. The improvement in electrical performance of the graphene sheets is explained in terms of the doping of graphene sheets caused by the charge transfer between the deposited metal and the graphene and thereby modified density of states for electrical conduction. Metal deposition also leads to the increased interlayer interaction of the graphene sheets as revealed by the transmission electron microscopy analysis. Further, two types of breakdown behaviors viz. sharp and stepped breakdowns observed for these graphene devices are explained in terms of the effective graphene-metal contact area. These studies reveal the implications of top metal contact fabrication on graphene for electronic devices.

Investigation of Metal-Induced Enhancement in Electrical Conductance of Multiwalled Carbon Nanotubes

We here segregate the contributions of contact improvement and change in multiwalled carbon nanotubes (MWNT) inherent properties in electrical conductance enhancement caused by metal deposition. The conductance of individual MWNTs enhances greatly due to the platinum and tungsten deposition even at the locations of the tube where no beneath metal contact is present. The change in conductance is explained in terms of the change in the density of states at Fermi level, due to charge transfer between metal atoms and nanotube as well as by radial stress created on the tube. This type of improved conduction is different from the high bias-assisted tunneling type carrier transport and in our study, even at zero bias an increment of 140% in the typical conductance value has been experimentally observed. These results are important for electronic device perspective of nanowire research, mainly the interconnect applications in real electronic devices.

Healing of Broken Multiwalled Carbon Nanotubes Using Very Low Energy Electrons in SEM: A Route Toward Complete Recovery

We report the healing of electrically broken multiwalled carbon nanotubes (MWNTs) using very low energy electrons (3-10 keV) in scanning electron microscopy (SEM). Current-induced breakdown caused by Joule heating has been achieved by applying suitably high voltages. The broken tubes were examined and exposed to electrons of 3-10 keV in situ in SEM with careful maneuvering of the electron beam at the broken site, which results in the mechanical joining of the tube. Electrical recovery of the same tube has been confirmed by performing the current-voltage measurements after joining. This easy approach is directly applicable for the repairing of carbon nanotubes incorporated in ready devices, such as in on-chip horizontal interconnects or on-tip probing applications, such as in scanning tunneling microscopy.

Ge n + /p junctions using temperature-based phosphorous implantation

This work compares the impact of implantation temperature ranging from cryogenic (-100 °C) to hot (400°C) on the performance of n+/p Ge junctions. Cryogenic implantation on bulk, planar Ge followed by a 400°C rapid thermal anneal leads to higher activation. lower junction depth, lower sheet resistance and lower junction leakage compared to RT and hot (400°C) implantation. The improved junction performance translates into higher ON current and lower OFF leakage for cryo implanted planar Ge n-MOSFETs. On the other hand, high dose/energy cryogenic implants on Ge fins are shown to degrade fin recrystallization due to the absence of a crystalline core because of increased amorphization. Crystallinity of as-implanted Ge fins indicates that hot implantation could be a more viable n+/p junction formation process for Ge FinFET technology.