Adam Osseiran

A Review of Current Neuromorphic Approaches for Vision, Auditory, and Olfactory Sensors

Conventional vision, auditory, and olfactory sensors generate large volumes of redundant data and as a result tend to consume excessive power. To address these shortcomings, neuromorphic sensors have been developed. These sensors mimic the neuro-biological architecture of sensory organs using aVLSI (analog Very Large Scale Integration) and generate asynchronous spiking output that represents sensing information in ways that are similar to neural signals. This allows for much lower power consumption due to an ability to extract useful sensory information from sparse captured data. The foundation for research in neuromorphic sensors was laid more than two decades ago, but recent developments in understanding of biological sensing and advanced electronics, have stimulated research on sophisticated neuromorphic sensors that provide numerous advantages over conventional sensors. In this paper, we review the current state-of-the-art in neuromorphic implementation of vision, auditory, and olfactory sensors and identify key contributions across these fields. Bringing together these key contributions we suggest a future research direction for further development of the neuromorphic sensing field.

Use of AHP in decision-making for machine tool configurations

Purpose The purpose of this paper is to develop a model of analytic hierarchy process (AHP), a multiple criteria decision-making method, to assist selecting suitable machine configurations for special purpose machines (SPMs) from available alternatives. Design/methodology/approach The necessary criteria and sub-criteria were identified and used in the developed model. The assessment process was carried out by constructing the hierarchy of four levels. Then, pairwise comparison matrices were created for each level to compute the weights for the alternatives. The model was programmed and implemented by software for practical use. Findings Different scenarios were obtained from the assessment process of the developed AHP model showing the influence of changing the relevant importance of the elements in the hierarchy on the selection of SPMs configurations. Selection of the suitable scenario was also affected by some factors of manufacturing preferences and industry recommendations such as cost and production rate. Originality/value This is a new application of AHP method which assists decision makers to select suitable configurations for SPMs, and reduce the time required for designing SPMs.

A Jittered-Sampling Correction Technique for ADCs

Jittered sampling raises the noise floor in Analogue to Digital Converters (ADCs). This leads to a decrease in its Signal to Noise ratio (SNR) and its effective number of bits (ENOB). This extended abstract proposes a technique that compensate for the effects of sampling with a jittered clock. A novel technique based on phase demodulation of the clock oscillator and Taylor series approximation is proposed to counter the effects of clock jitter in ADCs. Since jitter is caused by phase noise, phase demodulation provides a good estimate of the instantaneous jitter. A VLSI implementation of Taylor series is used to predict the input signal value at the correct time instant.

Vlsi-Soc: From Systems To Silicon

Testing is used to ensure high quality chip production. High test quality implies the application of high quality test data; however, the technology development has lead to a need of an increasing test data volume to ensure high test quality. The problem is that the test data volume has to fit the limited memory of the ATE (Automatic Test Equipment). In this paper, we propose a test data truncation scheme that for a modular core-based SOC (System-on-Chip) selects test data volume in such a way that the test quality is maximized while the selected test data is guaranteed to met the ATE memory constraint. We define, for each core as well as for the system, a test quality metric that is based on fault coverage, defect probability and number of applied test vectors. The proposed test data truncation scheme selects the appropriate number of test vectors for each individual core based on the test quality metric, and schedules the transportation of the selected test data volume on the Test Access Mechanism such that the system-s test quality is maximized and the test data fits the ATE-s memory. We have implemented the proposed technique and the experimental results, produced at reasonable CPU times, on several ITC-02 benchmarks show that high test quality can be achieved by a careful selection of test data. The results indicate that the test data volume (test application time) can be reduced to about 50% while keeping a high test quality.

Assembly modelling approach for special purpose machines

Purpose The purpose of this paper is to develop an assembly modelling approach to be applied with a software package, to assist in the design and assembly of special purpose machines (SPMs). Design/methodology/approach A database of SPM elements was established, and an assembly relationships graph was created. Mating conditions were identified between the SPM elements, and their assembly constraints were extracted and implemented in SolidWorks application programming interface. Findings The implementation of this assembly modelling approach was validated by selecting SPM layouts as examples. A significant reduction in the assembly time was achieved compared to the traditional assembly procedure for the same examples. Originality/value This is a new application of assembly modelling that assists engineers and designers in the design and assembly processes of SPMs. This approach can also be applied to other machine tools with similar attributes.

A Novel MicroPhotonic Structure for Optical Header Recognition

In this paper, we propose and demonstrate a new MicroPhotonic structure for optical packet header recognition based on the integration of an optical cavity, optical components and a photoreceiver array. The structure is inherently immune to optical interference thereby routing an optical header within optical cavities to different photo receiver elements to generate the autocorrelation function, and hence the recognition of the header using simple microelectronic circuits. The proof-of-concept of the proposed MicroPhotonic optical header recognition structure is analysed and experimentally demonstrated, and results show excellent agreement between measurements and theory.

An Investigation into Spike-Based Neuromorphic Approaches for Artificial Olfactory Systems

The implementation of neuromorphic methods has delivered promising results for vision and auditory sensors. These methods focus on mimicking the neuro-biological architecture to generate and process spike-based information with minimal power consumption. With increasing interest in developing low-power and robust chemical sensors, the application of neuromorphic engineering concepts for electronic noses has provided an impetus for research focusing on improving these instruments. While conventional e-noses apply computationally expensive and power-consuming data-processing strategies, neuromorphic olfactory sensors implement the biological olfaction principles found in humans and insects to simplify the handling of multivariate sensory data by generating and processing spike-based information. Over the last decade, research on neuromorphic olfaction has established the capability of these sensors to tackle problems that plague the current e-nose implementations such as drift, response time, portability, power consumption and size. This article brings together the key contributions in neuromorphic olfaction and identifies future research directions to develop near-real-time olfactory sensors that can be implemented for a range of applications such as biosecurity and environmental monitoring. Furthermore, we aim to expose the computational parallels between neuromorphic olfaction and gustation for future research focusing on the correlation of these senses.

Oscillation Built-In-Self-Test for ADC linearity testing in deep submicron CMOS technology

This paper proposes an Oscillation BIST (OBIST) that is meant to test ADCs fabricated in sub 100nm processes. The design is intended to be capable of testing a 10-bit ADC that was designed in 40nm CMOS. The design scheme presents a simple analog stimulus generator that was designed in 40nm CMOS together with schematic based simulation results. There is also a description of a calibration circuit and a highlevel implementation of a BIST control system to run the BIST and to calculate static parameters such as Differential Non-linearity (DNL) and Integral Non-linearity (INL). Simulation results for the analog stimulus generator suggest that OBIST might still be a viable method to test ADCs despite device scaling to sub 100nm processes.

Extending the test paradigm beyond the technology dissemination

The escalating demand for technology integration in and around CMOS devices and the introduction of a large variety of new processes and structures to achieve challenging new product features is yielding new systems with an increasing level of test complexity. This test technique can be easily incorporated in the current digital test techniques using ATE (Automated Test Equipment) and therefore allowing economical large scale production testing of devices combining electrical and optical signals.

Closing the testing gap between CMOS and photonics

High speed circuits and systems in their vast majority are still invariably based on CMOS technology for obvious cost and power efficiency reasons. Photonics science is gaining momentum in these high speed systems and is traditionally found in telecommunications but also in high performance computing and recently in standard computing systems with the main objective of alleviating the CPU to memory bottleneck. RF processing is producing another level of complexity in the new emerging variety of embedded mixed-signals circuits and systems where a signal changes its media types several times without leaving the package assembly. This new paradigm where RF, analogue, digital and optical signals are integrated in one component entails an ad-hoc testing and hierarchical fault modelling approaches that embrace the individual approaches of each of these signal types and amalgamate them into one optimised approach.