Adam Postula

Lowering power consumption in clock by using globally asynchronous locally synchronous design style

Power consumption in clock of large high performance VLSIs can be reduced by adopting globally asynchronous, locally synchronous design style (GALS). GALS has small overheads for the global asynchronous communication and local clock generation. We propose methods to (a) evaluate the benefits of GALS and account for its overheads, which can be used as the basis for partitioning the system into optimal number/size of synchronous blocks, and (b) automate the synthesis of the global asynchronous communication. Three realistic ASICs, ranging in complexity from 1 to 3 million gates, were used to evaluate GALS benefits and overheads. The results show an average power saving of about 70% in clock with negligible overheads.

Cell placement by self-organisation

Abstract Cell placement is an important step in the physical design of VLSI circuits. The problem with present day algorithms is their inherent sequential nature and inability to efficiently exploit massively parallel architectures. This paper formulates cell placement as a self-organisation problem and presents the result of such an attempt. We use an adaptation of Kohonens algorithm for self-organisation as it is well suited for implementation on massively parallel architectures. The placement problem is simplified by assuming cells to be of uniform width and the cost to be minimised as total weighted wire length. The results are compared to a similar experiment in cell placement. The algorithm is a general optimisation technique and has been successfully applied to other areas of VLSI CAD like scheduling and state assignment. “Birds of a feather, flock together”

A high resolution smart camera with GigE Vision extension for surveillance applications

Intelligent video surveillance is currently a hot topic in computer vision research. The goal of intelligent video surveillance is to process the captured video from the monitored area, extract specific information and take appropriate action based on that information. Due to the high computational complexity of vision tasks and the real-time nature of these systems, current software-based intelligent video surveillance systems are unable to perform sophisticated operations. Smart cameras are a key component for future intelligent surveillance systems. They use embedded processing to offload computationally intensive vision tasks from the host processing computers and increasingly reduce the required communication bandwidth and data flows over the network. This paper reports on the design of a high resolution smart camera with a GigE vision extension for automated video surveillance systems. The features of the new camera interface standard, GigE Vision will be introduced and its suitability for video surveillance systems will be described. The surveillance framework for which the GigE vision standard has been developed is presented as well as a brief overview of the proposed smart camera.

Effect of line of sight propagation on capacity of an indoor MIMO system

In this paper the performance of a multiple input multiple output (MIMO) wireless communication system operating in an indoor environment, featuring both line of sight (LOS) and non-line of sight (NLOS) signal propagation, is assessed. In the model the scattering objects are assumed to be uniformly distributed in an area surrounding the transmitting and receiving array antennas. Mutual coupling effects in the arrays are treated in an exact manner. However interactions with scattering objects are taken into account via a single bounce approach. Computer simulations are carried out for the system capacity for varying inter-element spacing in the receiving array for assumed values of LOS/NLOS power fraction and signal to noise ratio (SNR).

Genetic engineering versus natural evolution: genetic algorithms with deterministic operators

Genetic algorithms (GA) have several important features that predestine them to solve design problems. Their main disadvantage however is the excessively long run-time that is needed to deliver satisfactory results for large instances of complex design problems. The main aims of this paper are (1) to demonstrate that the effective and efficient application of the GA concept to design problem solving requires substitution of the basic GAs natural evolution by genetic engineering (GE), (2) to propose and discuss the concept of a genetic engineering algorithm (GEA), and (3) to show how to apply the GEA to solve synthesis problems. In this paper, an effective and efficient GE scheme is proposed and applied to solve an important design problem: the minimal input support problem. In almost all cases, our GEA produces strictly optimal results and realizes a very good trade-off between effectiveness and efficiency. The experimental results clearly demonstrate that the proposed GE scheme is suitable for solving design problems and its application results in very effective and efficient GEAs.

System Level Virtual Prototyping of DSP SOCs Using Grammar Based Approach

As we move from algorithm on a chip to system on a chip era, the design bottleneck is shifting from individual DSP functions to global control that composes a system from these functions. The practice in industry suffers from global control entering the design flow too late, discontinuity between functional modeling and implementation phase and mixing data flow with global control. MASIC—Maths to ASIC—is a methodology proposed in this paper that targets DSP SOCs and addresses these issues. Global control is specified in a grammar notation and integrates the output of functional modeling phase, the DSP functions, by referencing them. A virtual prototype is automatically built from such a specification that models the global control in VHDL and cosimulates with the DSP functions in C from the functional modeling phase. A highly efficient verification methodology based on separating the verification of global control from DSP functions is proposed. A smooth path to cycle true implementation is possible using either behavioral synthesis, IPs for the DSP functions or manual implementation. Experiments using realistic examples like GSM base band processing, rake receiver and some smaller examples have been carried out to quantify the benefits of MASIC.

Directional space-time oriented gradients for 3d visual pattern analysis

Various visual tasks such as the recognition of human actions, gestures, facial expressions, and classification of dynamic textures require modeling and the representation of spatio-temporal information. In this paper, we propose representing space-time patterns using directional spatio-temporal oriented gradients. In the proposed approach, a 3D video patch is represented by a histogram of oriented gradients over nine symmetric spatio-temporal planes. Video comparison is achieved through a positive definite similarity kernel that is learnt by multiple kernel learning. A rich spatio-temporal descriptor with a simple trade-off between discriminatory power and invariance properties is thereby obtained. To evaluate the proposed approach, we consider three challenging visual recognition tasks, namely the classification of dynamic textures, human gestures and human actions. Our evaluations indicate that the proposed approach attains significant classification improvements in recognition accuracy in comparison to state-of-the-art methods such as LBP-TOP, 3D-SIFT, HOG3D, tensor canonical correlation analysis, and dynamical fractal analysis.

FPGA based custom computing machines for irregular problems

Over the past few years there has been increased interest in building custom computing machines (CCMs) as a way of achieving very high performance on specific problems. The advent of high density field programmable gate arrays (FPGAs), in combination with new synthesis tools, have made it relatively easy to produce programmable custom machines without building specific hardware. In many cases, the performance achieved by a FPGA based custom computer is attributed to the exploitation of massive concurrency in the underlying application. In this paper we explore the sources of speedup for irregular problems in which is difficult to exploit such parallelism. We highlight 5 main sources of speedup that we have observed, namely the provision of high memory bandwidth, the use of flexible address generation hardware, the use of gather-scatter array operations, the use of lookup tables and the use of multiple tailored arithmetic units. By considering some representative examples of such irregular problems, the paper illustrates that good performance is possible given the current generation of FPGA devices and RISC processors. The paper then explores whether this performance gain will be possible given the next generation of RISC processors and FPGAs. It concludes that the only way to maintain the speedup is to alter the architecture of CCMs in combination with architectural changes to the FPGAs themselves.

Synthesis of custom interleaved memory systems

This paper presents a novel approach to the synthesis of interleaved memory systems that is especially suited for application-specific processors. Our synthesis system generates the optimized interleaved memories for a specific algorithm and finds the best mapping of arrays in that algorithm onto the memory system to achieve high performance. The design space is four-dimensional (4-D) and comprises the number of memory banks, the type of memory components, the storage scheme, and the range of clock period in the system. Optimal designs are found among the Pareto points (a set of nondominated points in the design space) computed for our memory model under the performance and cost criteria set by the designer. The memory model includes all the components of an interleaved memory system and covers a lookup table-based address generation with data alignment. The synthesis is based on a general periodic storage scheme, which enables efficient handling of irregular and overlapped access patterns. The synthesis process is the exhaustive search of the heavily pruned design space, and the pruning is based on mathematically proven properties of periodic storage schemes. This paper presents the theorems, the synthesis algorithm, and the methods of effective word and bank address generation. Examples are given to illustrate the effectiveness of our method.

A Wireless Sensor Node Architecture Using Remote Power Charging, for Interaction Applications

The wireless sensor node architecture proposed in this paper is optimized for use in a wireless interactive point, listen and see system. In particular, we focus on developing a wireless sensor node that can be remotely charged by harvesting microwave energy. The current system implementation allows a user to access information from a remote sensor via their mobile computing device. These sensors are limited in complexity due to the limited power available, and are cumbersome since manual intervention is required to replace its batteries. We propose a system where battery powered wireless sensor nodes can be recharged by harvesting energy from a microwave Radio Frequency (RF) signal source. The remote power charging module of the wireless sensor node architecture consisted of an antenna array and a rectification circuit. A prototype of the antenna array and rectification circuit of the remote power charging module for the wireless sensor node was constructed and is presented in this paper.