Adel Dokhanchi

On-Line Monitoring for Temporal Logic Robustness

In this paper, we provide a Dynamic Programming algorithm for on-line monitoring of the state robustness of Metric Temporal Logic specifications with past time operators. We compute the robustness of MTL with unbounded past and bounded future temporal operators (MTL\(^{<+\infty}_{+pt}\)) over sampled traces of Cyber-Physical Systems. We implemented our tool in Matlab as a Simulink block that can be used in any Simulink model. We experimentally demonstrate that the overhead of the MTL\(^{<+\infty}_{+pt}\) robustness monitoring is acceptable for certain classes of practical specifications.

Mining parametric temporal logic properties in model-based design for cyber-physical systems

One of the advantages of adopting a model-based development process is that it enables testing and verification at early stages of development. However, it is often desirable to not only verify/falsify certain formal system specifications, but also to automatically explore the properties that the system satisfies. In this work, we present a framework that enables property exploration for cyber-physical systems. Namely, given a parametric specification with multiple parameters, our solution can automatically infer the ranges of parameters for which the property does not hold on the system. In this paper, we consider parametric specifications in metric or Signal Temporal Logic (MTL or STL). Using robust semantics for MTL, the parameter mining problem can be converted into a Pareto optimization problem for which we can provide an approximate solution by utilizing stochastic optimization methods. We include algorithms for the exploration and visualization of multi-parametric specifications. The framework is demonstrated on an industrial size, high-fidelity engine model as well as examples from related literature.

Metric interval temporal logic specification elicitation and debugging

In general, system testing and verification should be conducted with respect to formal specifications. However, the development of formal specifications is a challenging and error prone task, even for experts. This is especially true when considering complex spatio-temporal requirements in real-time embedded systems, mixed-signal circuits, or more generally, software-controlled physical systems. In this work, we present a framework for the elicitation and debugging of formal specifications. The elicitation of formal specifications is handled through a graphical user interface. The debugging algorithm checks inconsistent and wrong specifications. Namely, it detects validity, redundancy and vacuity issues in formal specifications developed in a fragment of Metric Interval Temporal Logic (MITL). The algorithm informs system engineers on any issues in their specifications. This improves the specification elicitation process and, ultimately, the testing and verification process. Finally, we present experimental results on specifications that typically appear in Cyber Physical Systems (CPS) applications. Application of our specification debugging tool on user derived requirements shows that the aforementioned issues are common. Therefore, the algorithm can help developers to correct their specifications and avoid wasted effort on checking incorrect requirements.

Requirements driven falsification with coverage metrics

Specication guided falsication methods for hybrid systems have recently demonstrated their value in detecting design errors in models of safety critical systems. In specication guided falsication, the correctness problem, i.e., does the system satisfy the specication, is converted into an optimization problem where local negative minima indicate design errors. Due to the complexity of the resulting optimization problem, the problem is solved iteratively by performing a number of simulations on the system. Even though it is theoretically guaranteed that falsication methods will eventually find the bugs in the system, in practice, the performance of these methods, i.e., how many tests/simulations are executed before a bug is detected, depends on the specication, on the system and on the optimization method. In this paper, we define and utilize coverage metrics on the state space of hybrid systems in order to improve the performance of the falsication methods.

Feasibility Study of Using the RF Interconnects in Large FPGAs to Improve Routing Tracks Usage

In this paper, we explore the use of coplanar waveguide interconnects in FPGAs to improve wire delay and reduce the number of used routing tracks. We propose a new FPGA architecture in which RF receivers and transmitters are employed. In addition, we present an algorithm to re-route some suitable wires with RF interconnects. Experimental results show that using this technique, required routing tracks are reduced by 7% on average, and the delay of wire segments that use RF resources is decreased by 69.4%. These benefits are earned in cost of area and power consumption overhead that are negligible for large FPGAs.

Formal Requirement Debugging for Testing and Verification of Cyber-Physical Systems

A framework for the elicitation and debugging of formal specifications for Cyber-Physical Systems is presented. The elicitation of specifications is handled through a graphical interface. Two debugging algorithms are presented. The first checks for erroneous or incomplete temporal logic specifications without considering the system. The second can be utilized for the analysis of reactive requirements with respect to system test traces. The specification debugging framework is applied on a number of formal specifications collected through a user study. The user study establishes that requirement errors are common and that the debugging framework can resolve many insidious specification errors.

An efficient algorithm for monitoring practical TPTL specifications

We provide a dynamic programming algorithm for the monitoring of a fragment of Timed Propositional Temporal Logic (TPTL) specifications. This fragment of TPTL, which is more expressive than Metric Temporal Logic, is characterized by independent time variables which enable the elicitation of complex real-time requirements. For this fragment, we provide an efficient polynomial time algorithm for off-line monitoring of finite traces. Finally, we provide experimental results on a prototype implementation of our tool in order to demonstrate the feasibility of using our tool in practical applications.

Performance Improvement of Physical Retiming with Shortcut Insertion

Retiming is a well known method for improving the performance of sequential circuits. However, maximum cycle ratio (MCR) is one of the most serious restrictions to be considered by retiming-based techniques. As MCR is proportional to the critical cycle delay, finding shortcut paths to reduce the length of critical cycle can improve the circuit performance. In this paper, Shannon decomposition is used iteratively to insert shortcuts and reduce critical cycles delay. Reducing MCR can lead to better physical retiming results due to available placement information. Our experimental results show more than 16% improvement in retiming gained performance with the area overhead of about 3%, on average.