Adel Ghazel

Efficient FPGA implementation of Gaussian noise generator for communication channel emulation

In this paper, a high accuracy Gaussian noise generator emulator is defined and optimized for hardware implementation on a FPGA. The proposed emulator is based on the Box-Muller method implemented by using ROM tabulation and a random memory access. By means of accumulations, the central limit method is applied to the Box-Muller output Gaussian distribution. After presenting the algorithmic method, this paper analyzes its efficiency for different noise signal formats. Then the architecture to fit into a FPGA is explained. Finally, results from the FPGA synthesis are given to show the value of this method for FPGA implementation.

Design of High Speed AWGN Communication Channel Emulator

This paper presents a method for designing a high accuracy white gaussian noise generator suitable for communication channel emulation. The proposed solution is based on the combined use of the Box-Muller method and the central limit theorem. The resulting architecture provides a high accuracy AWGN with a low complexity architecture for a digital implementation in FPGA. The performance is studied by means of MATLAB simulations and various complexity figures are given.

A New Mode-Multiplexing LINC Architecture to Boost the Efficiency of WiMAX Up-Link Transmitters

This paper proposes a new amplifier architecture based on the outphasing technique intended for the efficiency enhancement of linear amplification with nonlinear components (LINC) transmitters. The proposed mode-multiplexing linear amplification with nonlinear components (MM-LINC) scheme operates according to the LINC concept for input signal magnitude drive levels below a certain threshold and as a balanced amplifier beyond this threshold. The setting of this threshold level influences the performance of the amplifier in terms of average power-added efficiency and linearity. A 2-W up-link transmitter prototype for worldwide interoperability for microwave access (WiMAX) applications was designed using this new architecture and optimized for a WiMAX signal with an 11.3-dB peak-to-average power ratio. The experimental results revealed a significant increase in power-added efficiency, from 6% for a LINC transmitter to 21% for the MM-LINC amplifier, while maintaining an error vector magnitude value under 8%, which is compliant with the standard requirement

Design and performance analysis of a high speed AWGN communication channel emulator

A hardware white Gaussian noise generator (WGNG) is developed in an FPGA circuit for mobile communication channel emulation. High accuracy, fast and low-cost hardware are reached by combining the Box-Muller and central limit methods. The performance of the designed model is investigated using MATLAB. The complexity and the performance level are given for some configurations and show the interest of the proposed model.

Power and efficiency enhancement of 3G multicarrier amplifiers using digital signal processing with experimental validation

This paper proposes a digital signal-processing-based approach suitable for the performance optimization of third-generation (3G) amplifiers in terms of spectrum and power. A peak-to-average power ratio (PAPR) reduction method, which is coding and modulation independent, based on peak clipping and digital filtering techniques, is proposed. Moreover, the multibranch memory polynomial pre-distorter identified with an optimized recursive least square technique was efficiently implemented in a digital signal processor. The cascade of the proposed PAPR reduction technique with the memory pre-distorter results in a substantial enhancement of the power amplifier (PA) output linear power and efficiency, while still meeting the 3G partnership project standard requirements. An experimental validation carried out on a 90-W laterally diffused metal-oxide-semiconductor PA, which was fed with a wide-band code-division multiple-access signal, led to a 4-dB rise in output mean linear power accompanied with 60% increase in its power-added efficiency.

On the RF/DSP design for efficiency of OFDM transmitters

In this paper, a system-level RF/digital signal processing (DSP) design approach of power-efficient orthogonal frequency-division multiplexing (OFDM) transmitters is proposed. A DSP-based low-IF architecture, which allows a significant enhancement of their power and spectrum efficiencies, is proposed. The cascade of the peak-to-average power ratio (PAPR) reduction technique, predistortion technique, and the in-phase and quadrature modulation led to impressive improvement in the power efficiency and effective linear output power of the OFDM transmitter. Measurement results carried out on an IEEE 802.11a transmitter designed and built for this experiment are presented in terms of error vector magnitude (EVM), adjacent channel leakage ratio, and power efficiency. The power stage of this transmitter uses a heterojunction bipolar InGaP transistor operating in a deeply class AB. The cascade of the PAPR reduction and baseband predistortion processing modules results in the reduction of the power backoff operation point by approximately 10 dB accompanied by a relative increase in the wireless local area network transmitter power efficiency by roughly 400% while meeting the emission mask spectrum and EVM levels demanded by the 802.11a standard.

On design and implementation of a decimation filter for multistandard wireless transceivers

In this work, we deal with the design and implementation of a decimation filter to be used in wideband radio-frequency receiver. The paper outlines architecture considerations for multistandard wireless transceivers. Also, it describes the design steps and the tradeoffs concerning the hardware implementation. GSM and DECT standards specifications are met by the proposed filtering cascade structure. The filter processes six-bit data stream input from a fourth-order sigma-delta modulator and has been prototyped in a field-programmable gate array device.

Optimized multistandard RF subsampling receiver architecture

This paper presents a novel subsampling-based down-conversion topology for multistandard radio receiver design. This receiver topology is based on two subsampling stages. The first stage has a fixed RF subsampling frequency; however, the IF sampling frequency of the second stage is variable and depends on the standard being considered. This approach overcomes various undesirable effects related to the sampling frequencies and noise aliasing. By optimizing the choice of the RF subsampling clock frequency, complete multistandard RF bands are down-converted to the same IF band. Quadrature baseband channel downconversion is achieved by a tunable IF sampling frequencies clock. A tunable band-pass RF filter and an IF band-pass filter are designed to perform anti-aliasing and limit wideband noise. A generic design methodology is proposed and validated through its application to a GSM, UMTS and IEEE-802.11g multistandard receiver. Simulation results of this receiver design example confirm the validation of proposed subsampling receiver topology and show the efficiency of the design methodology.

Statistical Characterization of the Indoor Low-Voltage Narrowband Power Line Communication Channel

This paper presents a novel statistical characterization of the indoor low-voltage (LV) narrowband power line communication (PLC) channel in CENELEC and FCC/ARIB bands. Experimental measurements of electrical network complex transfer functions were used to determine, for the frequency range up to 500 kHz, the statistics of the average channel gain, the delay spread parameters, the coherence bandwidth and the channel capacity. The average measured channel attenuation exhibits values between 16.36 and 26.95 dB with a mean of 20.75 dB in the frequency band from 10 to 500 kHz. The root mean square (rms) delay spread has a mean value of 2.12 μs with 90% of the channels revealing values below 3.20 μs. The minimum coherence bandwidth at 0.9 correlation level is of 1.23 kHz and the mean channel capacity is of 5.32 Mbps. The lognormal behavior is confirmed and justified for the rms delay spread but not for the average channel gain. The negative correlation between these two parameters is examined, and the relationships between the different studied metrics are also explored.

Correlated power noise generator as a low cost DPA countermeasures to secure hardware AES cipher

To secure cryptography hardware implementation many works are focusing on side-channels attacks. For such attacks, several different countermeasures can be done at different levels abstraction. But all published countermeasures lead to a significant area and power consumption overhead. In this paper, we present a new countermeasure against DPA attack which also leads to very small implementation compared to existing countermeasures such as the most used: masking schemes. The proposed approach is to use a correlated power noise generator to removes the design power correlation with the secret key. Its efficiency is proved with a practical DPA attack realization on Actel Fusion FLASH FPGA and Xilinx Virtex 4 SRAM FPGA. With the proposed countermeasures, the full 128-bits AES implementation on Xilinx Virtex 4 has a smaller area overhead (12.78 times less) than masking scheme countermeasures.