Adel Kalboussi

Analysis of photogenerated random telegraph signal in single electron detector (photo-SET)

In this paper, we analyzed slow single traps, situated inside the tunnel oxide of small area single electron photo-detector (photo-SET or nanopixel). The relationship between excitation signal (photons) and random-telegraph-signal (RTS) was evidenced. We demonstrated that photoinduced RTS observed on a photo-detector is due to the interaction between single photogenerated charges that tunnel from dot to dot and current path. Based on RTS analysis for various temperatures, gate bias and optical power we determined the characteristics of these single photogenerated traps: the energy position within the silicon bandgap, capture cross section and the position within the Si/SiO(x = 1.5) interfaces.

Electrical characteristics and modelling of multi-island single-electron transistor using SIMON simulator

In this paper, we present a multi-island single-electron transistor (MISET) model based on the orthodox theory and solving the master equation. Using SIMON simulator, we investigate the electrical characteristics of single-electron transistors (SETs) based on multiple islands and show the temperature dependence of the Coulomb oscillation of the SET with one to six islands as a function of gate voltage Vg in the temperature range from T=5 to 50K. Values of current tend to increase proportionally with temperature. For a high drain voltage, the MISET behaved as a single-island device. This is probably because the multiple islands were electrically enlarged and merged into a single island owing to the high applied drain voltage. Finally, we compare the advantages of MISET face to single-island SETs with identical dimensions of islands.

Macro-modeling for the compact simulation of single electron transistor using SIMPLORER

In this paper we present analog and digital studies of the single electron transistor (SET), in which only one electron at the time is transferred through the circuit. In the first part of this paper, we show numerical simulations of fundamental characteristics of SET using MATLAB. As a second part of this work we develop a closely example of macro-model of SET using SIMPLORER. Our idea to concept this macro-model was based on the quantification of the output signal on the island level. In order to obtain a quantified output signal on the island we have modeled a quantum dots as a quantizer bloc. This signal quantified was correlated to the energy levels. This description of a model let us to valid our conception and to value the impact of quantizer bloc on the output response of the SET.

A new SIMPLORER model for single-electron transistors

In the first part of this paper, we present simulations of single-electron transistor (SET) output characteristic using Maple. Typical SET I-V characteristics and charge energies curves are presented by developing Maple programs. In the second part of this work, we develop a new model without considering quantum effects using the superposition theorem, transfer function and Laplace transformer. Finally, we propose a new bloc using SIMPLORER 7.0 simulator to modulate quantum effects in the SET island. This model is based on a parallel analog-digital converter.

Electrical characteristics of metal–insulator–semiconductor and metal–insulator–semiconductor–insulator–metal capacitors under different high-k gate dielectrics investigated in the semi-classical and quantum mechanical models

In this paper the electrical characteristics of metal–insulator–semiconductor (MIS) and metal–insulator–semiconductor–insulator–metal (MISIM) capacitors with (100)-oriented p-type silicon as a substrate under different high- k gate dielectrics (SiO2, HfO2, La2O3 and TiO2) are investigated in the semi-classical and quantum mechanical models. We review the quantum correction in the inversion layer charge density for p-doped structures. The purpose of this paper is to point out the differences between the semi-classical and quantum mechanical charge descriptions at the insulator–semiconductor interface and the effect of the type of oxide and their position (gate oxide or buried oxide) in our structures. In particular, capacitance–voltage (C– V), relative position of the sub-band energies and their wavefunctions are studied to examine qualitatively and quantitatively the electron states and charging mechanisms in our devices. We find that parameters such as threshold voltage and device trans-conductance are enormously sensitive to the proper treatment of quantization effects.

Direct exchange between silicon nanocrystals and tunnel oxide traps under illumination on single electron photodetector

In this paper we present the trapping of photogenerated charge carriers for 300 s resulted by their direct exchange under illumination between a few silicon nanocrystals (ncs-Si) embedded in an oxide tunnel layer (SiOx = 1.5) and the tunnel oxide traps levels for a single electron photodetector (photo-SET or nanopixel). At first place, the presence of a photocurrent limited in the inversion zone under illumination in the I–V curves confirms the creation of a pair electron/hole (e–h) at high energy. This photogenerated charge carriers can be trapped in the oxide. Using the capacitance-voltage under illumination (the photo-CV measurements) we show a hysteresis chargement limited in the inversion area, indicating that the photo-generated charge carriers are stored at traps levels at the interface and within ncs-Si. The direct exchange of the photogenerated charge carriers between the interface traps levels and the ncs-Si contributed on the photomemory effect for 300 s for our nanopixel at room temperature.

Drain current model for single electron transistor operating at high temperature

A simple compact model was proposed to simulate the drain current characteristic for single electron transistor at high temperature, it takes into account all contributions mechanisms; thermionic and tunnel effects. Good agreement was reached with experimental results for temperatures up to 430 K. It is valuable for devices with multiple gates and symmetric or asymmetric structures. This result is suitable for fully SET or hybrid SET / CMOS circuits.

Effect of vehicular technology on energy consumption and emissions

Sustainable development requires inter al the reduction of energy consumption and of traffic-induced pollutant emissions. Hybrid electric vehicles (HEVs) are one of the most promising approaches to decrease emissions. This paper considers the influence of hybridization of transport on energy consumption and emissions on single lanes of road traffic. We have developed a micro-simulation tool which integrates instantaneous consumption and emission models. We have modelled microscopic behaviour of vehicles using a full velocity difference model for longitudinal moving. Then, we have used two macroscopic energy consumption models (COPERT and HBEFA) and an instantaneous energy-consumption model concerning the conventional Internal Combustion Engine (ICE) vehicle to illustrate the relevance of microscopic modelling of energy consumption. Furthermore, we have compared the energy consumption of the HEV Toyota Prius with that of the conventional ICE vehicle. An emission model emissions from traffic (EMIT) was also implemented and extended in order to estimate HEV emissions. The model is used to quantify CO2 and CO emissions for the HEV Toyota Prius and the conventional ICE vehicle. Moreover, we have studied the influence of fleet hybridization level on energy consumption for congested and uncongested traffic flow state. HEVs can offer major environmental improvements as well as substantial reductions of energy consumption and road traffic emissions. Hybridization is a relevant solution to reduce energy consumption and emissions.

Investigation of the kink effect in indium–doped silicon for sub 100 nm N channel MOSFET technology

The increasing interest in nanoelectronic devices that require cryogenic temperatures to function has led to an increased need for analog CMOS circuits. Using indium, an acceptor dopant in silicon, a heavy atom with a low diffusion coefficient is potentially suitable for doping the channel of CMOS transistors. These transistors when operated at low temperatures at which the majority of carriers experience freeze–out exhibit an effect known as the kink effect. In this paper, we will discuss the kink effect presented in the drain current–voltage measurement curves at low temperature. The variation of conductance and transconductance was calculated from measurements of the drain current versus gate and drain voltages. Capacitance–voltage versus temperature was measured to investigate the freeze–out of carriers that could be related to indium in the p–type doping region and then Deep Level Transient Spectroscopy (DLTS) measurement was carried out to determine the trap level and its activation energy. The effect of traps related to indium in Si NMOS transistors is investigated with the DLTS technique and the existence of a relationship between the kink effect and the active indium trap level situated at 0.18 eV from valence band is also discussed.

Study and modelling hybrid MTJ/Ring memory using SIMON Simulator

In this paper, we briefly suggest and describe the function of a new memory cell named hybrid MTJ/Ring memory. It is a perfect example of two features combination to obtain new functionalities that are difficult to achieve using either a pure MTJ or Ring memory cell alone. We present and discuss their characteristics simulated by SIMON Simulator in order to improve the access process for writing and/or reading single electron memory (SEM).