Adel Soudani

Low power hardware-based image compression solution for wireless camera sensor networks

In this paper, we present and evaluate a hardware solution for user-driven and packet loss tolerant image compression, especially designed to enable low power image compression and communication over wireless camera sensor networks (WCSNs). The proposed System-on-Chip is intended to be designed as a hardware coprocessor embedded in the camera sensor node. The goal is to relieve the node microcontroller of the image compression tasks and to achieve high-speed and low power image processing. The interest of our solution is twofold. First, compression settings can be changed at runtime (upon reception of a request message sent by an end user or according to the internal state of the camera sensor node). Second, the image compression chain includes a (block of) pixel interleaving scheme which significantly improves the robustness against packet loss in image communication. We discuss in depth the internal hardware architecture of the encoder chip which is planned to reach high performance running in FPGAs and in ASIC circuits. Synthesis results and relevant performance comparisons with related works are presented. We study a low power hardware solution for image compression in wireless camera sensor network. The goal is to relieve the node microcontroller of the image compression tasks and to achieve low-power image processing. We discuss the internal hardware architecture of the proposed encoder circuit and its implementation. We provide relevant comparisons with related solutions.

IEEE 802.11 Load Balancing: An Approach for QoS Enhancement

With the 802.11 WLAN multimedia applications (Video, Audio, real-time voice over IP,…) increasing, providing Quality of Service (QoS) support becomes very important since the original standard doesn’t take QoS into account. The standard offers access to the wireless users only regarding physical considerations. This can lead to overloaded access points (AP) and considerable degradation of the QoS. This paper deals with this problem. It focuses on the presentation of a QoS management solution for wireless communication systems. It mainly defends that a balanced distribution of mobile stations among the available access points leads to better performances of the Wireless LAN. Some OPNET simulations of the proposed approach are presented to show a better resources allocation and efficiency on QoS metrics. A protocol structure between mobiles and APs is also specified for the implementation of this approach. An SDL description and MSC simulation of this protocol is provided as a first step in its development.

An approach for end-to-end QoS and network resources management

Abstract In this paper, we address the problem of the end-to-end QoS management for multimedia and real-time applications. We would focus on the presentation of a multi-profile communication environment and its reliability in ensuring end-to-end QoS management in the network communication processes. This communication environment, called Virtual Communication Support (VCS), provides a dynamic assignment of application requirements to the network resources reservation and protocol layers invocation. The advantage of this model is that it performs the capabilities of the network by abstracting the details of all communication stacks-layers that must be invoked in the communication process from application specificities and needs. A great attention is devoted to the end-to-end QoS management in the VCS communication model. We would present our approach for the development of a transport middleware for end-to-end QoS control. This middleware performs the QoS management with an adaptive and predictive algorithm based on the network jitter measurement. The main contribution of this paper is that it provides a solution to predict congestion during communication process and then it can avoid network overloading. This is of several importances when we are streaming multimedia real-time packets. In fact, when real-time application losses some packets it may lead to unfavorable situations. Our approach for the specification and the design of the middleware is based on the use of the Specification and Description Language (SDL). This is a formal description technique that enables model validation extension and reusability. The dynamic behavior of this model is being checked with the Message Sequence Chart (MSC). The simulation and validation of this middleware was performed for the VCS. It was simulated by The Network Simulator (NS). Some profiles with the JAVA language on the Fast-Ethernet Local Area Network. Its testing was performed for a real-time manufacturing process and multimedia supervision for control processes.

Efficient Physical Modeling of MEMS Energy Harvesting Devices With VHDL-AMS

In this paper, we propose a VHDL-AMS implementation of a physical model of a microelectromechanical systems (MEMS) piezoelectric microgenerator. Such an executable model acts as a bridge between specifications and fabricated devices. Usually, physical and geometrical parameters of electromechanical parts of a system are only considered in lower levels of the design flow, typically using finite-element tools, which, despite their accuracy, do not allow efficient optimization of the structure properties and dimensions. Thus, it would be very interesting to have a model of the entire harvesting system (the MEMS piezoelectric microgenerator cascaded with the electronic circuit) to perform efficient optimization. Some features like damping effects and process fluctuations have considerable impact on the performance of MEMS, especially the resonant structures. We propose a method of integrating such features early in the design flow, while keeping the simulation time reasonable. The resulting model is reusable, predictive (comparable to experimental results) and respects Kirchhoff laws. Consequently, it can be integrated in global simulation of multidomain and mixed signal systems like wireless sensor nodes.

Design and performance analysis of a zonal DCT-based image encoder for Wireless Camera Sensor Networks

Systems mapped on CMOS architectures are often expected to achieve high processing bandwidth and low energy consumption. However, a specific care should be paid to adequate the algorithm structure to the circuit architecture when designing multimedia wireless embedded networking systems. This paper addresses the problem of low power consumption and real time constraints for image communication in wireless camera sensor networks (WCSN). It presents a low-complexity hardware implementation of JPEG-like encoder for image compression and paquetization. The designed circuit is planned to be embedded in the camera sensor node to relieve the main processor of the data processing tasks. This encoder combines the best lifting DCT algorithm of the literature with a zonal coding approach. The former reduces the number of operations required per DCT coefficient while the latter reduces the number of coefficients to be computed, quantized and encoded. We study the tradeoff between the size of the zonal mask (a square zone of size k) and the visual image quality as a function of the compression bitrate, then we describe the hardware features of the JPEG-like circuit when implemented on different FPGAs and ASIC prototypes. Performance evaluation is provided for several ranges of compression bitrate, accordingly with the right value of k. Considering a grayscale image compressed to 0.25bpp for example, k=4 is the best choice. In this case, and for an image of 128x128 pixels, the CMOS circuit of the proposed encoder, synthesized using 45nm integration technology, clocks at 360MHz and consumes 18.02mW. It outperforms most of similar circuits being presented in the literature.

FPGA-based image compression for low-power Wireless Camera Sensor Networks

In this paper, a low-complexity image compression scheme for energy-constrained Wireless Camera Sensor Networks (WCSN) is presented and its hardware implementation cost for FPGA solution is evaluated. The main purpose of this FPGA circuit is to relieve the main microcontroller in the camera sensor node of the image compression tasks and to achieve highspeed and low-power image processing. The interest of our hardware solution is twofold. First, a fast zonal DCT algorithm is used to reduce the number of DCT coefficients in each block of the image to be computed, quantized and encoded. Second, compression settings can be changed at runtime in order to allow a dynamic adjustment of the trade-off between energy consumption and image distortion. The efficiency of the image compression scheme is validated through experimental results using FPGA platform.

QoS and network resources management for communication in distributed manufacturing processes

In this paper, we present a multimedia communication model based on the virtual manufacturing device (VMD) concept that has been defined in the international manufacturing message specification (MMS). This model called the virtual communication support (VCS), makes it possible to cohabit different communication techniques, such as ATM and ethernet, provides a multiprofile solution to introduce real-time multimedia applications and manages network resources. Its specification and design used to perform workstation capabilities to avoid network bottleneck. For these purposes, it defines a service set between the application layer and the other communication layers to manage network resources reservation negotiate the quality of service (QoS) and ensure real-time service execution. The design of this communication model is based on the idea of the specification and description language (SDL) use. It is a formal description technique that enables model validation, extension and reusability. The dynamic behavior of this model is being checked with the message sequence chart (MSC).The implementation and the experimentation of this VCS model are being achieved using the JAVA language. It is being done on the fast-ethernet local area network equipped with multimedia and manufacturing devices.

Efficient hardware solution for low power and adaptive image-compression in WSN

In this paper, we present and evaluate a hardware implementation for user-driven and packet-loss tolerant image compression, especially designed to enable low-power image compression and communication over wireless sensors networks (WSNs). The proposed compression scheme, presented as a CMOS circuit, is intended to be embedded in the camera sensor. It will be considered as a co-processor for tasks related with image compression and data packetization, which unloads the main microcontroller so that it will spend less time in active mode. The interest of our solution is twofold. First, compression settings can be changed at runtime (upon reception of a request message sent by an end-user or according to the internal state of the camera sensor node). Second, the image compression chain includes a (block of) pixel interleaving scheme which significantly improves the robustness against packet loss in image communication. The main part of this paper focuses on the specification and the performances analysis of this solution when implemented on FPGA and ASIC circuits.

Image-Based object identification for efficient event-driven sensing in wireless multimedia sensor networks

Applications based on video and image in wireless sensor network are highly attractive due to their wealth of information. In this context, application for object recognition and tracking using image and video information is one the attractive approaches that can be applied for event detection and localization, security processes, following of the rare animal species and control of road traffic, and so forth. However, the implementation of such approach with WMSN requires a specific image processing scheme and efficient transmission protocol. In fact, because of the limited energy of the batteries embedded in motes, the power consumption is the major constraint facing network life time and reliability in WMSN. The efficiency and the validity of these multimedia applications over wireless sensor networks are then dependent on the capabilities of the designer to provide low-power scheme for data processing and energy-aware transmission protocols. This paper presents a contribution to the design of low complexity scheme based on object identification for efficient sensing of multimedia information in wireless multimedia sensor networks. It proposes a new solution and explores the associated performances of this scheme. The presented results in this paper attest the high efficiency to achieve low-power objects identification when implemented in wireless motes.

Contribution to the design of a CMOS image sensor with low-complexity video compression for wireless sensor networks

Demand for low-power sensing devices with integrated image processing capabilities is increasing, especially for resource-constrained systems such as WSNs. CMOS technology enables the integration of image sensing and image processing, which improves the overall system performance. The aim of this paper is to present and evaluate a smart image sensor integrating a user-driven video compression scheme designed to respect the energy constraints of image processing and transmission over WSNs. The interest of our solution is twofold. First, compression settings can be changed at run time depending on video characteristics. Second, compression is applied only on blocks that change significantly over time. This paper presents in details the internal hardware architecture of the proposed system and describes its performance, with relevant comparisons to some related works.