Adin Hyslop

Cosmic ray neutron induced upsets as a major contributor to the soft error rate of current and future generation DRAMs

The system soft error rate (SSER) of 4M/16M DRAMs has been shown to be dependent on the cosmic ray neutron flux. A simple model and accelerated soft error rate (ASER) measurements made with an intense, high energy neutron beam support this result. The model predicts that cosmic ray neutron induced soft errors will become important at the 64M DRAM generation and beyond.

An analytical method for determining intrinsic drain/source resistance of lightly doped drain (LDD) devices

Abstract MOS devices with double diffusion junctions containing Lightly Doped Drain/Source (LDD) regions have been built and analyzed. Comparison of current characteristics of the 2 μ m LDD devices with conventional devices of same channel length indicates that the LDD devices, while displaying relatively good drain current gain, deviate from the MOS transistors in the linear region due to the intrinsic n− drain/source resistance and thus have lower substrate current due to the reduced hot electron effects. An analytical method is developed where this intrinsic resistance can be extracted from curve fitting of I–V data. Through curve fitting analysis the intrinsic resistance parameter is found to be an inverse function of transistor width as well as being dependent on temperature in the usual T 3 2 manner.

Impact of Hot Carriers on Dram Circuits

Hot carrier stress degradation in MOSFETs is well known but its impact on DRAM circuit functionality has not been thoroughly investigated. In this paper observed DRAM degradation with stress is related to the actual transistor level degradation. It is shown here that the transistor saturation drain current is a good monitor of the DRAM Access Time, while the Precharge Time and the Refresh Time can be related respectively to degradations in the transistors linear drive current and the saturation region subthreshold current. As concluded in this paper, transistor parameters other than just Vt and gm need to be monitored with hot carrier stress to understand the full impact on DRAM circuit functionality.

Inverse current gain improvement of bipolar transistors by double-base diffusion

The double-base diffusion process is introduced and is experimentally shown to significantly improve the inverse or upward current gain of the n-p-n bipolar transistor. The technique consists of a deep p+diffusion into an external base region of multicollector transistors forming a close-in collar around the intrinsic base of each transistor. This technique, together with the use of deep diffusion n+guard rings around the complete unit cell, is shown to improve the inverse current gain significantly.