Adit D. Singh

Interstitial redundancy: an area efficient fault tolerance scheme for large area VLSI processor arrays

In the proposed scheme, spare PEs are located at interstitial sites within the array. Each spare can functionally replace any one of the neighboring primary PEs that are connected to it. Because spares are physically close to the PE that they replace, restructured interconnections are short, minimizing performance degradation. This structure can incorporate different levels of redundancy depending on how many of the interstitial sites are used to locate spares, and also how many spares are placed at each site. The author gives a polynomial time algorithm for assigning operational spares to failed primary PEs. He also gives area efficient layouts for such structures, and designs for implementing the switching network needed for reconfiguration. A procedure for deciding the optimum level of redundancy so as to maximize chip area utilization is also shown. The main attractive features of interstitial redundancy are short (fixed length) PE interconnections and high utilization of failure-free PEs. The analysis shows that for a wide range of array sizes and PE survival probabilities, 45-55 percent utilization of failure-free PEs on the chip can be achieved. >

On implementing large binary tree architectures in VLSI and WSI

The authors present an efficient scheme for the layout of large binary-tree architectures by embedding the complete binary tree in a two-dimensional array of processing elements. Their scheme utilizes virtually 100% of the processing elements in the array as computing elements; it also shows substantial improvements in propagation delay and maximum edge length over H-tree layouts. They shown that their layouts readily lend themselves to fault-tolerant designs for overcoming fabrication defects in large-area and wafer-scale implementations of binary-tree architectures. >

On Optimizing Wafer-Probe Testing for Product Quality Using Die-Yield Prediction

We propose a new adaptive testing procedure that uses spatial defect clustering information to optimize test lengths during wafer-probe testing. For the same average test lengths, our approach shows better than a factor-of-two improvement in average defect levels. It further allows the separation of high-quality dies with defect levels more than an order of magnitude better than the average for the production run. Our proposal is orthogonal to all other approaches for improving defect quality and can be combined with them.

An efficient channel routing algorithm for defective arrays

Although a number of defect-tolerance schemes for two-dimensional VLSI/WSI (wafer scale integration) processor arrays have been proposed in the literature, none is efficient enough always to guarantee a restructured array that utilizes all the good processors on the wafer while using only a limited number of interconnection channels. The authors present a restructuring scheme that can achieve this (no matter how severely clustered the faults) with a maximum channel width of three, provided the total number of faults in the array are within some stated limits. For practical size arrays, this limit is large enough so as not be be restrictive in practice. Moreover, the scheme also works extremely well, in a probabilistic sense, for a larger number of faults, when the failed processors are severely clustered.<<ETX>>

Near optimal embedding of binary tree architecture in VLSI

An efficient scheme is presented for embedding a complete binary tree architecture in a two-dimensional array of processing elements. The scheme utilizes almost 100% of the processing elements in the array as actual computing elements, with small and asymptotically optimal propagation delay. The maximum edge length is optimal for trees with up to six levels. The scheme is compared with other designs proposed in the literature and shown to be significantly better.<<ETX>>

A modular fault-tolerant binary tree architecture with short links

The authors present a novel modular fault-tolerant binary tree architecture which is shown to be more effective in overcoming both operational faults and fabrication defects than earlier approaches. Furthermore, for practical size trees of up to eight levels, it is shown how the proposed design can be efficiently load out in VLSI with very short interconnections. Thus, the design is suitable for monolithic implementation of a large binary tree architectures. For board level multichip designs, a hybrid scheme, combining the new design with the SOFT approach, is presented. It shows better reliability than either design alone. >

Adaptive voting for fault (VFF) node scheme for distributed self-diagnosis

Distributed self-diagnosis has long been proposed to efficiently test multiprocessor and array based systems. Such an approach is also now being considered for testing integrated circuit wafers containing identical circuits. Here the testing is based on a majority voting on the test results from neighboring nodes. The authors identify that the voting for faulty node (VFF) always performs better than the voting for good node (VFG), irrespective of the number of voting cells and fault rate. Based on the VFF approach, an approach to find the optimal number of tests allowing the most accurate test results is proposed. The authors also introduce an adaptive voting scheme by which the time overhead of the traditional voting schemes can be significantly reduced.

AN EFFICIENT RESTRUCTURING APPROACH FOR WAFER SCALE PROCESSOR ARRAYS

Parallel processing using processor arrays is being widely investigated to overcome the performance limitations of traditional uniprocessor computer systems. Some inherent problems with the board level implementation of highly parallel systems are separate component packaging costs, assembly cost on printed circuit boards, and low reliability due to the complex pin to pin interconnections on the boards. Especially significant is the large signal propagation delay in MOS VLSI technology required to drive signals off chip. Wafer Scale Integration (WSI)1 promises a solution to this problem by integrating the entire processor array and the interconnection structure on a single packaged wafer. Thus WSI will make it possible to eliminate the off chip signal drivers required within the processor chips, and the complex board level interconnections among the processors. As a result, signal delays can be substantially reduced allowing faster operation. In addition, system reliability may also be improved because of elimination of the mechanical and electrical failures frequently observed at the pins and interconnections in traditional designs.

Four-valued interface circuits for NMOS VLSI

Abstract In this paper we present radix 4 to binary encoder and decoder interface circuits for NMOS VLSI. The circuits can be implemented using standard binary NMOS fabrication processes and are designed to operate correctly over the entire target range of device parameters specified by MOSIS. They have been simulated using SPICE with the typical parameters provided by MOSIS, and found to work correctly. Thus these circuits can be readily used to reduce pinouts of binary NMOS logic chips, and thereby allow significant cost savings.

A new processor interconnection structure for fault tolerant processor arrays

Processor arrays integrated on a wafer can display a high performance mainly due to the short communication delay between processors. However, an efficient fault tolerance scheme is essential to yield the desired array because some components on wafer can be defective. In this paper, the authors present a new processor interconnection structure which requires much less chip area than the traditional design for restructuring a rectangular array. Because interconnection of a fault tolerant processor array occupies a substantial chip area, especially for large word parallel systems, this will significantly improve the overall performance of the processor arrays in VLSI/WSI.<<ETX>>