Adnan Aziz

Model-checking continuous-time Markov chains

We present a logical formalism for expressing properties of continuous-time Markov chains. The semantics for such properties arise as a natural extension of previous work on discrete-time Markov chains to continuous time. The major result is that the verification problem is decidable; this is shown using results in algebraic and transcendental number theory.

Verifying Continuous Time Markov Chains

We present a logical formalism for expressing properties of continuous time Markov chains. The semantics for such properties arise as a natural extension of previous work on discrete time Markov chains to continuous time. The major result is that the verification problem is decidable; this is shown using results in algebraic and transcendental number theory.

It Usually Works: The Temporal Logic of Stochastic Systems

In this paper the branching time logic pCTL* is defined. pCTL* expresses quantitative bounds on the probabilities of correct behavior; it can be interpreted over discrete Markov processes. A bisimulation relation is defined on finite Markov processes, and shown to be sound and complete with respect to pCTL*. We extend the universe of models to generalized Markov processes in order to support notions of refinement, abstraction, and parametrization. Model checking pCTL* over generalized Markov processes is shown to be elementary by a reduction to RCF. We conclude by describing practical and theoretical avenues for further work.

Simultaneous routing and buffer insertion with restrictions on buffer locations

During the routing of global interconnects, macro blocks form useful routing regions which allow wires to go through but forbid buffers to be inserted. They give restrictions on buffer locations. In this paper, we take these buffer location restrictions into consideration and solve the simultaneous maze routing and buffer insertion problem. Given a block placement defining buffer location restrictions and a pair of pins (a source and a sink), we give a polynomial time exact algorithm to find a buffered route from the source to the sink with minimum Elmore delay.

On Combining Formal and Informal Verification

We propose algorithms which combine simulation with symbolic methods for the verification of invariants. The motivation is two-fold. First, there are designs which are too complex to be formally verified using symbolic methods; however the use of symbolic techniques in conjunction with traditional simulation results in better “coverage” relative to the computational resources used. Additionally, even on designs which can be symbolically verified, the use of a hybrid methodology often detects the presence of bugs faster than either formal verification or simulation.

BDD Based Procedures for a Theory of Equality with Uninterpreted Functions

The logic of equality with uninterpreted functions has been proposed for verifying abstract hardware designs. The ability to perform fast satisfiability checking over this logic is imperative for such verification paradigms to be successful. We present symbolic methods for satisfiability checking for this logic. The first procedure is based on restricting analysis to finite instantiations of the variables. The second procedure directly reasons about equality by introducing Boolean-valued indicator variables for equality. Theoretical and experimental evidence shows the superiority of the second approach.

Enhancing simulation with BDDs and ATPG

We introduce SImulation Verification with Augmentation (SIVA), a tool for checking safety properties on digital hardware designs. SIVB integrates simulation with symbolic techniques for vector generation. Specifically, the core algorithm uses a combination of ATPG and BDDs to generate input vectors which cover behavior not excited by simulation. Experimental results demonstrate considerable improvement in state space coverage compared with either simulation or formal verification in isolation.

Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations

A network-on-chip (NoC) replaces on-chip communication implemented by point-to-point interconnects in a multi-core environment by a set of shared interconnects connected through programmable crosspoints. Since an NoC may provide a number of paths between a given source and destination, manufacturing or runtime faults on one interconnect does not necessarily render the chip useless. It is partly because of this fault tolerance that NoCs have emerged as a viable alternative for implementing communication between functional units of a chip in the nanometer regime, where high defect rates are prevalent. In this paper, the authors quantify the fault tolerance offered by an NoC against process variations. Specifically, the authors develop an analytical model for the probability of failure in buffered global NoC links due to interconnect dishing, and effective channel length variation. Using the developed probability model, the authors study the impact of link failure on the number of cycles required to establish communications in NoC applications

Multicast scheduling for switches with multiple input-queues

We address the problem of serving multicast traffic in input-queued packet switches. Head-of-line blocking is a major problem in input-queued switches. It can be avoided in unicast switches by maintaining a queue per output port at each input port. This is not feasible in multicast switches, since the number of destination multicast addresses is exponential in the number of output ports. Our approach is to maintain a limited number of input queues for multicast traffic. We solve two key resulting problems: (1) how to assign incoming packets to queues, and (2) which packets should be selected to transfer to output queues. Through heuristic arguments and simulation we show that our architecture leads to significant improvements in switch throughput over the best existing scheduling algorithms. Since modern links operate at very high speeds, we take care to ensure that the scheduling algorithm can be implemented efficiently in hardware.

OC-3072 packet classification using BDDs and pipelined SRAMs

We present a solution to the problem of quickly classifying packets. Our approach is based on techniques from logic synthesis. Specifically, we express the classification rules as Boolean logic equations, build binary decision diagrams for these equations, and then map the BDDs to a logic network consisting of a pipeline of static RAM banks. We illustrate our approach by applying it to the longest prefix matching for IP forwarding, and present evidence that our scheme can perform a billion matches per second on a CAIDA backbone forwarding table containing 60,000 prefixes. We show how our approach generalizes to classifying packets on multiple fields.