Adolf Schöner

Deep Defect Centers in Silicon Carbide Monitored with Deep Level Transient Spectroscopy

Electrical data obtained from deep level transient spectroscopy investigations on deep defect centers in the 3C, 4H, and 6H SiC polytypes are reviewed. Emphasis is put on intrinsic defect centers observed in as-grown material and subsequent to ion implantation or electron irradiation as well as on defect centers caused by doping with or implantation of transition metals (vanadium, titanium, chromium, and scandium).

Nitrogen donors in 4H‐silicon carbide

Hall‐effect and infrared‐absorption measurements are performed on n‐type 4H‐SiC samples to investigate the energy positions of the ground state and the excited states of the nitrogen donor in the 4H polytype of silicon carbide. Two electrically active levels (Hall effect) and three series of absorption lines (infrared spectra) are assigned to two nitrogen donor species which substitute on the two inequivalent lattice sites (h,k) in 4H‐SiC. Valley‐orbit splitting of the ground‐state level of the nitrogen donors on hexagonal sites (h) is found to be equal to ΔEvo(h)=7.6 meV. It is shown that the energy position of excited states of both nitrogen donors can be calculated by the effective‐mass approximation by assuming anisotropic effective masses m⊥=0.18m0 and m∥=0.22m0. The influence of the two inequivalent lattice sites on the values of ionization energy and valley orbit splitting of the nitrogen donor ground‐state levels is discussed.

PHOSPHORUS-RELATED DONORS IN 6H-SIC GENERATED BY ION IMPLANTATION

Aluminum‐doped 6H‐SiC epilayers were implanted with phosphorus and subsequently annealed in a temperature range from 1400 to 1700 °C. The annealing behavior of implanted phosphorus atoms was studied by the Hall effect, admittance spectroscopy, and photoluminescence. Phosphorus acts as a shallow donor. Two ionization energies of (80±5) meV and (110±5) meV are determined, which are assigned to phosphorus atoms residing at hexagonal and cubic lattice sites, respectively. Assuming first‐order kinetics, the annealing process results in an activation energy of the phosphorus donors of 2.5 eV. A set of four lines at a wavelength of about 420/421 nm is observed in the low temperature photoluminescence spectra; the intensity of these lines increases in parallel with the electrical activation of phosphorus donors by raising the annealing temperature. It is proposed that these lines are phosphorus‐related.

Chemical vapor deposition and characterization of undoped and nitrogen‐doped single crystalline 6H‐SiC

Homoepitaxial growth of single crystalline 6H‐SiC layers is performed by chemical vapor deposition (CVD). 6H‐SiC substrates are grown by a sublimation technique. They have vicinal surfaces inclined 1.5° to 2° from the (0001) plane towards the [1100] direction. We report CVD growth at 1600 °C in the hydrogen‐silane‐propane gas system with nitrogen as a dopant. High quality films are achieved with growth rates of about 1.8 μm per hour. The layers are examined by optical microscopy, infrared reflection, photoluminescence, and Rutherford backscattering. For electrical characterization capacitance‐voltage and Hall measurements are performed. Unintentionally doped layers have donor concentrations in the upper 1015 cm−3 range. Electron mobilities of 370 cm2/V s at room temperature and about 104 cm2/V s at 45 K are observed. To the authors’ knowledge this is the highest mobility so far reported for 6H silicon carbide.

Tailoring the graphene/silicon carbide interface for monolithic wafer-scale electronics

Graphene is an outstanding electronic material, predicted to have a role in post-silicon electronics. However, owing to the absence of an electronic bandgap, graphene switching devices with high on/off ratio are still lacking. Here in the search for a comprehensive concept for wafer-scale graphene electronics, we present a monolithic transistor that uses the entire material system epitaxial graphene on silicon carbide (0001). This system consists of the graphene layer with its vanishing energy gap, the underlying semiconductor and their common interface. The graphene/semiconductor interfaces are tailor-made for ohmic as well as for Schottky contacts side-by-side on the same chip. We demonstrate normally on and normally off operation of a single transistor with on/off ratios exceeding 10(4) and no damping at megahertz frequencies. In its simplest realization, the fabrication process requires only one lithography step to build transistors, diodes, resistors and eventually integrated circuits without the need of metallic interconnects.

SiC power devices for high voltage applications

Abstract Silicon Carbide device technology is now evolving from a pure vision to a real alternative to silicon devices. The feasibility of SiC devices has been shown for many different types of devices, the development of a working production technology has started, yield, reliability and costs now being the key issues. At present the high substrate prices keep the manufacturing costs of SiC high, making it very difficult to enter the device market with SiC on economic terms. Prime applications are those for which SiC offers substantial benefits or even a technological breakthrough on the system level. The main application is power conversion where the latest development efforts on silicon based power switches (e.g. IGBT) allow utilisation of much higher switching frequencies, putting very high demands on the free wheeling diode. The system performance is to a large extent limited by the diode recovery charge—a major source of switching losses. Depending on the voltage range, different device concepts are of interest: In the lower voltage range the junction–barrier controlled Schottky (JBS) device is a promising candidate while at voltages beyond 2.5 kV the PIN diodes is the device of choice. Different system requirements—e.g. surge current capability—make the PIN junction superior to a Schottky device for certain applications. With progress in material and technology development the ‘world’s best’ result is becoming less and less important and reproducibility is the issue. Failure analysis of defective devices needs to be established with a high number of substrate defects being still an obstacle in SiC. High leakage/soft reverse characteristics are often encountered and can usually be attributed to localised defects. It is important to identify their origin and to separate process-induced defects from those already present in the epilayer or substrate. In order to use the high power handling capability of SiC reduction of margins (e.g. in epilayer thickness and doping) is necessary. This requires narrow bandwidth of process and material variations. For paralleling of SiC devices equal current sharing under static and dynamic conditions is a fundamental requirement from the system side. Top-down calculation gives material specifications, which the supplier has to meet.

Low Density of Interface States in n-Type 4H-SiC MOS Capacitors Achieved by Nitrogen Implantation

A surface-near Gaussian nitrogen (N) profile is implanted into n-type 4H-SiC epilayers prior to a standard oxidation process. Depending on the depth of the oxidized layer and on the implanted N concentration, the density of interface states DIT determined in corresponding 4H-SiC MOS capacitors decreases to a minimum value of approx. 1010 cm-2eV-1 in the investigated energy range (EC-(0.1 eV to 0.6 eV)), while the flat-band voltage increases to negative values due to generated fixed positive charges. A thin surface-near layer, which is highly N-doped during the chemical vapour deposition growth, leads to a reduction of DIT only close to the conduction band edge.

Geometrical effects in high current gain 1100-V 4H-SiC BJTs

This paper reports the fabrication of epitaxial 4H-SiC bipolar junction transistors (BJTs) with a maximum current gain /spl beta/=64 and a breakdown voltage of 1100 V. The high /spl beta/ value is attributed to high material quality obtained after a continuous epitaxial growth of the base-emitter junction. The BJTs show a clear emitter-size effect indicating that surface recombination has a significant influence on /spl beta/. A minimum distance of 2-3 /spl mu/m between the emitter edge and base contact implant was found adequate to avoid a substantial /spl beta/ reduction.

4H-SiC Power MOSFET Blocking 1200V with a Gate Technology Compatible with Industrial Applications

A normally off 4H-SiC power MOSFET blocking 1200 V is presented. Its structure, process and electrode materials are designed as close as possible to that of standard Si power MOSFETs, especially the gate electrode is made of pol ycrystalline silicon. The gate oxide is prepared by oxidation in nitrous oxide. In order to make the device compatible with standard gate drivers for power electronics the gate oxide thicknes s has been increased to 72 nm. With respect to long term stability the device is character ized at a maximum oxide field strength of 2.5 MV/cm. Onand off-state characteristics are presented and analy zed in detail. Introduction Improvements of the inversion layer mobility of 4H-SiC metal oxide semiconductor field effect transistors (MOSFETs) were reported recently by using gate oxide nitridation [1-4]. Values up to 48 cm/Vs resulted for lateral 4H-MOSFETs prepared on low doped p-type epilayers. This is remarkable since with thermal oxidation by oxy gen values below 1 cm /Vs were typical. For vertical MOSFETs 4H-SiC was seen as the worst choice from inversion channel mobility point of view, in spite of its high bulk mobility. As point ed out in [5], the inversion channel mobility strongly depends on the polytype. This effect i s most likely caused by carbon related surface states energetically fixed to around 2.9 eV above the valence band. Depending on the band gap of the polytype they act as near interface t raps, more or less overlapping with the conduction band edge. Consequently a higher channel mobility can be achieved using 15Rand 6H-SiC polytypes. But on the other hand the bulk mobilit y f 6HSiC parallel to the c-axis is much lower and makes 6H-SiC les s suitable for power devices. 15R-SiC would be the best choice but is not commercially available. This paper combines the method of forming a gate oxide by nitridation [ 1] with the technology developed for vertical SiC power MOSFETs described in [6]. In this case a polycrystalline silicon gate was used which is standard for sili con power MOSFET technology. Furthermore, the gate oxide thickness was significantly increased in order to meet the requirements of industrial power applications: compatibility wit h standard gate driving circuitry (gate source voltages within ±20 V) and long term stability obtained by strictly limiting the oxide field strength to 2.5 MV/cm. Device and Fabrication A cell structure of the so called triple implanted vertical MO SFET is sketched in Fig. 1. One can easily imagine that structure, process and electr od materials are designed as close as possible to the well known silicon DMOS. The device is planar and thus favora ble f fabrication. Characteristic design data are listed in Table 1. I n particular, if the inversion layer dominates the on-resistance it is important to achieve a gate le ngth as homogeneous as possible. For this purpose a self aligning process has been developed. The p-type body diode as well as the n-type source implantation of the MOSFET cell a re defined by only one mask. Materials Science Forum Online: 2003-09-15 ISSN: 1662-9752, Vols. 433-436, pp 769-772 doi:10.4028/www.scientific.net/MSF.433-436.769

Traps at the Interface of 3C-SiC/SiO2-MOS-Structures

Conductance method and admittance spectroscopy are employed to monitor t raps at the interface of differently processed 3Cand 4H-SiC/SiO 2 MOS capacitors. It is demonstrated that oxidation of 3C-SiC under NO-ambient leads to low values of the densi ty of interface states in the entire SiC band gap.