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Dive into the research topics where Adrián Pousa is active.

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Featured researches published by Adrián Pousa.


acm symposium on applied computing | 2015

ACFS: a completely fair scheduler for asymmetric single-isa multicore systems

Juan Carlos Saez; Adrián Pousa; Fernando Castro; Daniel Chaver; Manuel Prieto-Matías

Single-ISA (instruction set architecture) asymmetric multicore processors (AMPs) were shown to deliver higher performance per watt and area than symmetric CMPs (Chip Multi-Processors) for applications with diverse architectural requirements. A large body of work has demonstrated that this potential of AMP systems can be realizable via OS scheduling. Yet, existing schedulers that seek to deliver fairness on AMPs do not ensure that equal-priority applications experience the same slowdown when sharing the system. Moreover, most of these schemes are also subject to high throughput degradation and fail to effectively deal with user priorities. In this work we propose ACFS, an asymmetry-aware completely fair scheduler that seeks to optimize fairness while ensuring acceptable throughput. Our evaluation on real AMP hardware, and using scheduler implementations on a general-purpose OS, demonstrates that ACFS achieves an average 11% fairness improvement over state-of-the-art schemes, while providing better system throughput.


Journal of Parallel and Distributed Computing | 2017

Towards completely fair scheduling on asymmetric single-ISA multicore processors

Juan Carlos Saez; Adrián Pousa; Fernando Castro; Daniel Chaver; Manuel Prieto-Matías

Single-ISA asymmetric multicore processors (AMPs), which combine high-performance big cores with low-power small cores, were shown to deliver higher performance per watt than symmetric CMPs (Chip Multi-Processors). Previous work has highlighted that this potential of AMP systems can be realizable via OS scheduling. To date, most existing scheduling schemes for AMPs have been designed to optimize the system throughput, but they are inherently unfair. Although fairness-aware schedulers have been also proposed, they fail to effectively deal with user priorities and do not always ensure that equal-priority applications experience a similar slowdown. To overcome these limitations, we propose ACFS, an asymmetry-aware completely fair scheduler that seeks to optimize fairness while ensuring acceptable throughput. Our evaluation on real AMP hardware and using scheduler implementations in the Linux kernel demonstrates that ACFS achieves an average 23% fairness improvement over two state-of-the-art schemes, while providing higher system throughput. Throughput and fairness are largely conflicting optimization goals on AMPs.Previous asymmetry-aware schedulers fail to effectively deal with user priorities.ACFS achieves an average 23% fairness improvement over state-of-the-art schemes.Predicting cross-core performance on current AMPs is one of the major challenges.


european conference on parallel processing | 2014

Exploring the Throughput-Fairness Trade-off on Asymmetric Multicore Systems

Juan Carlos Saez; Adrián Pousa; Fernando Castro; Daniel Chaver; Manuel Prieto-Matías

Symmetric-ISA (instruction set architecture) asymmetric-performance multicore processors (AMPs) were shown to deliver higher performance per watt and area than symmetric CMPs (Chip Multi-Processors). Previous work has shown that this potential of AMP systems can be realizable thanks to the OS scheduler. Existing scheduling schemes that deliver fairness and priority enforcement on AMPs do not cater to the fact that applications in a multiprogram workload may derive different benefit from using fast cores in the system. As a result, they are likely to perform thread-to-core mappings that degrade the system throughput. To address this limitation, we propose Prop-SP, a scheduling algorithm that aims to improve the throughput-fairness trade-off on AMPs. Our evaluation on real hardware, and using scheduler implementations on a general-purpose OS, reveals that Prop-SP delivers a better throughput-fairness trade-off than state-of-the-art schedulers for a wide variety of multi-application workloads.


The Computer Journal | 2017

PMCTrack: Delivering Performance Monitoring Counter Support to the OS Scheduler

Juan Carlos Saez; Adrián Pousa; R. Rodriíguez-Rodriíguez; Fernando Castro; Manuel Prieto-Matías

Hardware performance monitoring counters (PMCs) have proven effective in characterizing application performance. Because PMCs can only be accessed directly at the OS privilege level, kernellevel tools must be developed to enable the end-user and userspace programs to access PMCs. A large body of work has demonstrated that the OS can perform effective runtime optimizations in multicore systems by leveraging performance-counter data. Special attention has been paid to optimizations in the OS scheduler. While existing performance monitoring tools greatly simplify the collection of PMC application data from userspace, they do not provide an architecture-agnostic kernel-level mechanism that is capable of exposing high-level PMC metrics to OS components, such as the scheduler. As a result, the implementation of PMC-based OS scheduling schemes is typically tied to specific processor models. To address this shortcoming we present PMCTrack, a novel tool for the Linux kernel that provides a simple architecture-independent mechanism that makes it possible for the OS scheduler to access per-thread PMC data. Despite being an OSoriented tool, PMCTrack still allows the gathering of monitoring data from userspace, enabling kernel developers to carry out the necessary offline analysis and debugging to assist them during the scheduler design process. In addition, the tool provides both the OS and the user-space PMCTrack components with other insightful metrics available in modern processors and which are not directly exposed as PMCs, such as cache occupancy or energy consumption. This information is also of great value when it comes to analyzing the potential benefits of novel scheduling policies on real systems. In this paper, we analyze different case studies that demonstrate the flexibility, simplicity and powerful features of PMCTrack.


The Computer Journal | 2018

On the Interplay Between Throughput, Fairness and Energy Efficiency on Asymmetric Multicore Processors

Juan Carlos Saez; Adrián Pousa; A. De Giusti; Manuel Prieto-Matías

Asymmetric single-ISA multicore processors (AMPs), which integrate highperformance big cores and low-power small cores, were shown to deliver higher performance per watt than symmetric multicores. Previous work has highlighted that this potential of AMP systems can be realizable by scheduling the various applications in a workload on the most appropriate core type. A number of scheduling schemes have been proposed to accomplish different goals, such as system throughput optimization, enforcing fairness or reducing energy consumption. While the interrelationship between throughput and fairness on AMPs has been comprehensively studied, the impact that optimizing energy efficiency has on the other two aspects is still unclear. To fill this gap, we carry out a comprehensive analytical and experimental study that illustrates the interplay between throughput, fairness and energy efficiency on AMPs. Our analytical study allowed us to define the energy-efficiency factor (EEF) metric, which aids the OS scheduler in identifying which applications are more suitable for running on the various cores to ensure a good balance between performance and energy consumption. We propose two energy-aware OS-level schedulers that leverage the EEF metric; the first one strives to optimize the energy-delay product (EDP), the second scheduler can be configured to optimize different metrics on the AMP. To demonstrate the effectiveness of these proposals, we performed an extensive evaluation and comparison with state-of-the-art schemes by using real asymmetric hardware and scheduler implementations in the Linux kernel.


international conference on theory and practice of electronic governance | 2016

Experiences with Electronic Vote: Challenges and Solutions

Patricia Mabel Pesado; Nicolás Galdámez; César Armando Estrebou; Adrián Pousa; Ismael Pablo Rodriguez; Sebastián Rodriguez Eguren; Franco Chichizola; Ariel C. Pasini; Armando Eduardo De Giusti

This paper presents results of a research on electronic voting carried out by the Institute of Research in Computer Science LIDI of the School of Computer Science of the National University of La Plata, Argentina, as part of research in e-Government developed since 2003. In particular, the topic of electronic vote has generated various experiences that allowed developing different election models for public and private environments. These experiences have resulted in the transfer of technology to several sectors


Archive | 2013

Performance Analysis of a Symmetric Cryptographic Algorithm on Multicore Architectures

Adrián Pousa; Victoria María Sanz; Armando Eduardo De Giusti


II Congreso de Tecnología en Educación y Educación en Tecnología | 2007

Laboratorio de procesamiento paralelo multi-cluster accesible vía web

Adrián Pousa; Armando Eduardo De Giusti; Marcelo Naiouf


XVII Congreso Argentino de Ciencias de la Computación | 2011

Análisis de rendimiento de un algoritmo de criptografía simétrica sobre arquitecturas multicore

Adrián Pousa; Victoria María Sanz; Armando Eduardo De Giusti


XIV Congreso Argentino de Ciencias de la Computación | 2008

E-learning: extensiones de los entornos virtuales para el manejo de actividades experimentales en Informática

María Cristina Madoz; Eduardo Ibañez; Adrián Pousa; Armando Eduardo De Giusti

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Franco Chichizola

National University of La Plata

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Marcelo Naiouf

National University of La Plata

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Laura Cristina De Giusti

National University of La Plata

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Ismael Pablo Rodriguez

National University of La Plata

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Victoria María Sanz

National University of La Plata

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Enzo Rucci

National University of La Plata

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Diego Miguel Montezanti

National University of La Plata

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Fernando Emmanuel Frati

National Scientific and Technical Research Council

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