Adrianus Marinus Gerardus Peeters

An asynchronous low-power 80C51 microcontroller

This paper presents a low-power asynchronous implementation of the 80C51 microcontroller. It was realized in a 0.5 /spl mu/ CMOS process and it shows a power advantage of a factor 4 compared to a recent synchronous implementation in the same technology. The chip is fully bit compatible with the synchronous implementation, and timing compatible for external memory access. The circuit is a compiled VLSI-program, using Tangram as VLSI-programming language and the Tangram tool-set to compile the design automatically to a standard-cell netlist. This design approach proves to be powerful enough to describe the microcontroller and derive an efficient implementation. Further, it offers the designer the possibility to explore various alternatives in the design space.

Stretching quasi delay insensitivity by means of extended isochronic forks

Handshake circuits can be mapped onto QDI circuits using generic standard-cells only. Despite several interesting optimizations, the resulting circuits are large. By extending the isochronic-fork assumption, we arrive at a class of asynchronous circuits that particularly allow efficient realizations of double-rail data paths. This paper defines the extended isochronic fork, discusses its implementation, and provides numerous examples. The impact on circuit costs is evaluated for a DCC error decoder. In an appendix a basic arbiter (mutual-exclusion element) is presented that requires simple CMOS gates only. We also propose a 3-way generalization of this arbiter.

A single-rail re-implementation of a DCC error detector using a generic standard-cell library

We present a fully asynchronous implementation of a DCC Error Detector. The circuit uses 4-phase handshake signaling and single-rail data encoding, and has been realized using standard cells from a generic cell library. The circuit is obtained by fully automatic translation from a high-level (Tangram) description, using handshake circuits as intermediate architecture. In comparison with a previous double-rail implementation the fabricated IC is 40% smaller (core area), three times faster, and consumes only a quarter of the power. Switching between two power supplies is described as a technique to reduce power dissipation even further. A comparative evaluation also includes an improved double-rail implementation and two synchronous circuits.

Adding synchronous and LSSD modes to asynchronous circuits

A synchronous mode as well as a scan mode of operation are added to a large class of asynchronous circuits, in compliance with LSSD design rules. This enables the application of mainstream tools for design-for-testability and test-pattern generation to asynchronous circuits. The approach is based on a systematic transformation of all single-output sequential gates into synchronous and scannable versions. By exploiting dynamic circuit operation in scan mode, the overhead of this transformation in terms of both circuit cost and circuit delay is kept minimal.

A multiplexer based test method for self-timed circuits

A new test method for self-timed circuits is presented that only uses multiplexers to make the majority of combinational feedback loops testable. Combinational feedback loops are problematic for testing, since they introduce sequential behavior in a circuit. Traditionally feedback loops are broken with scan latches or event scan flip-flops, which causes not only a large area overhead, but also has a large impact on performance. The method we present significantly reduces the cost of testing a self-timed circuit, while it retains all the benefits of traditional scan test methods. Most importantly, the method remains fully compatible with standard combinational test pattern generation tools and provides up to 100% stuck-at fault coverage. With the presented test method, it becomes cost effective to use scan test for a self-timed circuit without the need to add new specialized cells to a standard cell library.