Afandi Ahmad

An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores

This paper describes a dynamic partial reconfiguration (DPR) design flow and environment for image and signal processing algorithms used in adaptive applications. Based on the evaluation of the existing DPR design flow, important features such as overall flexibility, application and standardised interfaces, host applications and DPR area/size placement have been taken into consideration in the proposed design flow and environment. Three intellectual property (IP) cores used in pre-processing and transform blocks of compression systems including colour space conversion (CSC), two-dimensional biorthogonal discrete wavelet transform (2-D DBWT) and three-dimensional Haar wavelet transform (3-D HWT) have been selected to validate the proposed DPR design flow and environment. Results obtained reveal that the proposed environment has a better solution providing: a scriptable program to establish the communication between the field programmable gate array (FPGA) with IP cores and their host application, power consumption estimation for partial reconfiguration area and automatic generation of the partial and initial bitstreams. The design exploration offered by the proposed DPR environment allows the generation of efficient IP cores with optimised area/speed ratios. Analysis of the bitstream size and dynamic power consumption for both static and reconfigurable areas is also presented in this paper.

Rapid prototyping of AES encryption for wireless communication system on FPGA

This paper proposes a wireless communication system for secure transmission of data. Bluetooth is used as the wireless communication medium due to its low-cost and low-power consumption features. Advanced encryption standard (AES) protocol is implemented for the security reason over Bluetooth stack. RC10 prototyping board with Xilinx XC3S1500L-4-FG320 device has been used for the hardware evaluation of the system design. The system is configured to capture frames in real-time from the on-board OminiVision 9650 CMOS camera and transmit these frames securely via Bluetooths connectivity. On reception, the images are decrypted and displayed on the external monitor. The design has also been demonstrated for edge detection over the wireless communication channel. The overall design is evaluated in terms of resource utilisation and maximum operating frequency.

Efficient FPGA implementation of a wireless communication system using Bluetooth connectivity

The development of the security layers between the wireless terminals is one of the biggest trends in wireless communications. Bluetooth can be described as the short range and the low power supplements that holds the connection protocol through various devices. This paper presents the development of a secure wireless connection terminals on a field programmable gate array (FPGA). The wireless connection has been established using Bluetooth technology and the initialisation of a secure algorithm for data exchange is implemented using the advanced encryption standards (AES). The proposed system has been validated and demonstrated using using an image processing application which involves the encryption and decryption of acquired images from the RC10 FPGA prototyping boards cam-era. The evaluation of different building block has been carried out in terms of area, resources used and power consumption.

A novel feature vectors construction approach for face recognition

This paper discusses a novel feature vectors construction approach for face recognition using discrete wavelet transform (DWT). Four experiments have been carried out focusing on: DWT feature selection, DWT filter choice, features optimization by coefficients selection as well as feature threshold. In order to explore the most suitable method of feature extraction, different wavelet quadrant and scales have been studied. It then followed with an evaluation of different wavelet filter choices and their impact on recognition accuracy. An approach for face recognition based on coefficient selection for DWT is the presented and analyzed. Moreover, a study has been deployed to investigate ways of selecting the DWT coefficient threshold. The results obtained using the AT&T database have shown a significant achievement over existing DWT/PCA coefficient selection techniques and the approach presented increases recognition accuracy from 94% to 97% when the Coiflet 3 wavelet is used.

FPGA-based IP cores implementation for face recognition using dynamic partial reconfiguration

This paper presents a combination of novel feature vectors construction approach for face recognition using discrete wavelet transform (DWT) and field programmable gate array (FPGA)-based intellectual property (IP) core implementation of transform block in face recognition systems. Initially, four experiments have been conducted including the DWT feature selection and filter choice, features optimisation by coefficient selections and feature threshold. To examine the most suitable method of feature extraction, different wavelet quadrant and scales have been evaluated, and it is followed with an evaluation of different wavelet filter choices and their impact on recognition accuracy. In this study, an approach for face recognition based on coefficient selection for DWT is presented, and the significant of DWT coefficient threshold selection is also analysed. For the hardware implementation, two architectures for two-dimensional (2-D) Haar wavelet transform (HWT) IP core with transpose-based computation and dynamic partial reconfiguration (DPR) have been synthesised using VHDL and implemented on Xilinx Virtex-5 FPGAs. Experimental results and comparisons between different configurations using partial and non-partial reconfiguration processes and a detailed performance analysis of the area, power consumption and maximum frequency are also discussed in this paper.

Dynamic partial reconfiguration of 2-D Haar wavelet transform (HWT) for face recognition systems

This paper presents two novel architectures for two-dimensional (2-D) Haar wavelet transform (HWT) of transform block in face recognition systems. The proposed architectures comprises 2-D HWT with transpose-based computation and dynamic partial reconfiguration (DPR) that have been synthesised using VHDL and implemented on Xilinx Virtex-5 FPGAs. To evaluate the proposed architecture, comparison for both configurations and a detailed performance analysis in terms of area, power consumption and maximum frequency are also addressed in this paper.

Optimal discrete wavelet transform (DWT) features for face recognition

Face recognition systems usually include preprocessing, in order to crop the training and probe images. This often involves arbitrarily-chosen segmentation boundaries, which may exclude discriminative face information or include irrelevant pixels corresponding to background, hair, etc. The work presented in this paper creates a rich feature vector using discrete wavelet transform (DWT) coefficients, which is then optimized to exclude useless information. This optimization process eliminates the need to overly crop images, as background will be automatically excluded. Experiments on the AT&T database show that the technique improves results significantly, with recognition rates increasing from 93% to 97.5% when using the Haar wavelet.

A new approach of active compliance control via fuzzy logic control for multifingered robot hand

Safety is a vital issue in Human-Robot Interaction (HRI). In order to guarantee safety in HRI, a model reference impedance control can be a very useful approach introducing a compliant control. In particular, this paper establishes a fuzzy logic compliance control (i.e. active compliance control) to reduce impact and forces during physical interaction between humans/objects and robots. Exploiting a virtual mass-spring-damper system allows us to determine a desired compliant level by understanding the behavior of the model reference impedance control. The performance of fuzzy logic compliant control is tested in simulation for a robotic hand known as the RED Hand. The results show that the fuzzy logic is a feasible control approach, particularly to control position and to provide compliant control. In addition, the fuzzy logic control allows us to simplify the controller design process (i.e. avoid complex computation) when dealing with nonlinearities and uncertainties.

Rapid prototyping of neonatal jaundice detector using skin optics theory

When newborns present with jaundice, various clinical assessment need to be executed including evaluation of the history, physical examination, and assessment of severity of jaundice. This project concerns with the quantification of neonatal jaundice level using Simulink model-based design. It is important to address that the proposed method is non-invasive, hence suitable for infants. In this project, the concentration level of bilirubin in dermis layer of skin has been detected using skin optic theory with light emitting diode (LED) and photodiode as a detector. To evaluate the proposed system, a mock skin soaking is used to replace the real infants skin. At the system level, Arduino Uno has been used as a hardware platform, whilst MATLAB and Simulink have been fully utilised to implement the systems architecture. An evaluation of the proposed systems reveals its capability to detect, process and display real-time results with three (3) levels of jaundice, including normal, mild and critical.

Rapid prototyping of three-dimensional transform for medical image compression

This paper presents the design and implementation of three-dimensional (3-D) Haar and Daubechies with transpose based method for medical image compression. Due to the separability property of the multi-dimensional Haar and Daubechies, the proposed architecture has been implemented using a cascade of three N-point one-dimensional (1-D) Haar/Daubechies and two transpose memories for a 3-D volume of N×N×N suitable for real-time 3-D medical imaging applications. Two architectures were synthesised using VHDL and implemented on Altera®Cyclone II (EP2C15AF484C6) field programmable gate array (FPGA). Experimental results and an analysis of the area, power consumption and maximum frequency are discussed in this paper.