Afshin Abdollahi

A Robust Power Gating Structure and Power Mode Transition Strategy for MTCMOS Design

The large magnitude of supply/ground bounces, which arise from power mode transitions in power gating structures, may cause spurious transitions in a circuit. This can result in wrong values being latched in the circuit registers. We propose a design methodology for limiting the maximum value of the supply/ground currents to a user-specified threshold level while minimizing the wake up (sleep to active mode transition) time. In addition to controlling the sudden discharge of the accumulated charge in the intermediate nodes of the circuit through the sleep transistors during the wake up transition, we can eliminate short circuit current and spurious switching activity during this time. This is, in turn, achieved by reducing the amount of charge that must be removed from the intermediate nodes of the circuit and by turning on different parts of the circuit in a way that causes a uniform distribution of current over the wake up time. Simulation results show that, compared to existing wakeup scheduling methods, the proposed techniques result in a 1-2 orders of magnitude improvement in the product of the maximum ground current and the wake up time

A new canonical form for fast boolean matching in logic synthesis and verification

An efficient and compact canonical form is proposed for the Boolean matching problem under permutation and complementation of variables. In addition, an efficient algorithm for computing the proposed canonical form is provided. The efficiency of the algorithm allows it to be applicable to large complex Boolean functions with no limitation on the number of input variables as apposed to previous approaches, which are not capable of handling functions with more than seven inputs. Generalized signatures are used to define and compute the canonical form while symmetry of variables is used to minimize the computational complexity of the algorithm. Experimental results demonstrate the efficiency and applicability of the proposed canonical form.

An effective power mode transition technique in MTCMOS circuits

The large magnitude of supply/ground bounces, which arise from power mode transitions in power gating structures, may cause spurious transitions in a circuit. This can result in wrong values being latched in the circuit registers. We propose a design methodology for limiting the maximum value of the supply/ground currents to a user-specified threshold level while minimizing the wake up (sleep to active mode transition) time. In addition to controlling the sudden discharge of the accumulated charge in the intermediate nodes of the circuit through the sleep transistors during the wake up transition, we can eliminate short circuit current and spurious switching activity during this time. This is in turn achieved by reducing the amount of charge that must be removed from the intermediate nodes of the circuit and by turning on different parts of the circuit in a way that causes a uniform distribution of current over the wake up time. Simulation results show that, compared to existing wakeup scheduling methods, the proposed techniques result in a one to two orders of magnitude improvement in the product of the maximum ground current and the wake up time.

Probabilistic decision diagrams for exact probabilistic analysis

A decision diagram based framework is proposed for representing the probabilistic behavior of circuits with faulty gates. The authors introduce probabilistic decision diagrams (PDD) as an exact computational tool which along with vast expressive power holds many other useful properties such as space efficiency (on average) and efficient manipulation algorithms (polynomial in size.) An algorithm for constructing the PDD for a circuit is proposed. Useful information about probabilistic behavior of the circuit (such as output error probability for arbitrary input probability distribution) can be directly extracted from the PDD representation. Experimental results demonstrate the effectiveness and applicability of the proposed approach.

Analysis and Synthesis of Quantum Circuits by Using Quantum Decision Diagrams

Quantum information processing technology is in its pioneering stage and no proficient method for synthesizing quantum circuits has been introduced so far. This paper introduces an effective analysis and synthesis framework for quantum logic circuits. The proposed synthesis algorithm and flow can generate a quantum circuit using the most basic quantum operators, i.e., the rotation and controlled-rotation primitives. The paper introduces the notion of quantum factored forms and presents a canonical and concise representation of quantum logic circuits in the form of quantum decision diagrams (QDDs), which are amenable to efficient manipulation and optimization including recursive unitary functional bi-decomposition. This paper concludes by presenting the QDD-based algorithm for automatic synthesis of quantum circuits

Symmetry Detection and Boolean Matching Utilizing a Signature-Based Canonical Form of Boolean Functions

A compact canonical form and a computational procedure for solving the Boolean matching problem under permutation and complementation of variables are presented. The proposed approach, which utilizes generalized signatures and variable symmetries, can handle combinational functions with no limitation on the number of input variables. Experimental results demonstrate the generality and effectiveness of the proposed canonical form and the associated Boolean matching algorithm.

Signature based Boolean matching in the presence of don't cares

Boolean matching is to determine whether two functions are equivalent under input permutation and input/output phase assignment. This paper will address the Boolean Matching problem for incompletely specified functions. Signatures have previously been used for Boolean matching of completely specified functions. In this paper for the first time we use signatures to determine the equivalency of incompletely specified functions.

Leakage current reduction in sequential circuits by modifying the scan chains

Input vector control is an effective technique for reducing the leakage current of combinational VLSI circuits when these circuits are in the sleep mode. In this paper a design technique for applying the minimum leakage input to a sequential circuit is proposed. Our method uses the built-in scan-chain in a VLSI circuit to drive it with the minimum leakage vector when it enters the sleep mode. Using these scan registers eliminates the area and delay overhead of the additional circuitry that would otherwise be needed to apply the minimum leakage vector to the circuit. We show how the proposed technique can be used for several different scan-chain architectures and present the experimental results on the MCNC91 benchmark circuits.

Adaptive leakage control on body biasing for reducing power consumption in CMOS VLSI circuit

Power dissipation is an important issue in VLSI circuit design. This paper emphasizes on adaptive leakage control using body bias technique to reduce the power dissipation of the 65 nm MOS devices. Through adding forward body biasing, the leakage is reduced in sub-100 nm CMOS devices (unlike above-100 nm devices) while slightly increasing the signal propagation delay. For the conditions where the circuit does not use up the entire clock cycle, this slack can be used to reduce the power dissipation without any loss in performance. The fact that the circuit delay remains less than the clock period provides the opportunity to reduce power consumption of VLSI circuits. The objective is to change the voltage of the body bias to reduce leakage, allowing the circuit to consume less power whenever the clock edge can be met as detected beforehand.

Analysis and optimization of static power considering transition dependency of leakage current in VLSI circuits

We show that leakage current in VLSI circuits is not only a function of the current state (input combination) of a combinational circuit but also is dependent on the state history (previous input combinations). As an example application of the transition-dependent leakage model, we extend a known technique for calculating and applying the minimum leakage input vector to a combinational circuit in the standby mode to one which calculates and applies a pair of input vectors to initialize the circuit to the minimum leakage configuration.